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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:06:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:06:13 -0800 |
| commit | 2e51dc1856aae456e15cafd484997bfbd102175e (patch) | |
| tree | e446b57a8d99be177068c96e15e4f9753ec8b402 | |
| parent | b523ecf2f45f80488412781ba9a3455a71d64d62 (diff) | |
| download | yosys-2e51dc1856aae456e15cafd484997bfbd102175e.tar.gz yosys-2e51dc1856aae456e15cafd484997bfbd102175e.tar.bz2 yosys-2e51dc1856aae456e15cafd484997bfbd102175e.zip | |
verilog: ignore '&&&' when not in -specify mode
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 9 | ||||
| -rw-r--r-- | tests/various/specify.v | 6 |
3 files changed, 12 insertions, 5 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 9b43c250e..18fa2966b 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -440,7 +440,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { } "&&&" { - if (!specify_mode) REJECT; + if (!specify_mode) return TOK_IGNORED_SPECIFY_AND; return TOK_SPECIFY_AND; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 9b1b07f86..f37c6d99b 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -146,7 +146,7 @@ struct specify_rise_fall { %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY -%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND +%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED @@ -1117,6 +1117,7 @@ system_timing_arg : system_timing_args : system_timing_arg | + system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg | system_timing_args ',' system_timing_arg ; path_delay_expression : @@ -1137,9 +1138,9 @@ ignspec_constant_expression: ignspec_expr: expr { delete $1; } | expr ':' expr ':' expr { - delete $1; - delete $3; - delete $5; + delete $1; + delete $3; + delete $5; }; ignspec_id: diff --git a/tests/various/specify.v b/tests/various/specify.v index 5006e4c38..aa8aca4bc 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -51,3 +51,9 @@ specify $setuphold(d, posedge clk, 1:2:3, 4:5:6); endspecify endmodule + +module test5(input clk, d, e, output q); +specify + $setup(d, posedge clk &&& e, 1:2:3); +endspecify +endmodule |