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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-02-26 09:49:41 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-02-26 09:49:41 +0100 |
| commit | 80656ad17836a222f2359576d72f0b451c4ddfe6 (patch) | |
| tree | 4db39735399cc760b2928c7a6474839cd2deda00 | |
| parent | c1cee15d64ec2da29672d0f94610830d12793191 (diff) | |
| download | yosys-80656ad17836a222f2359576d72f0b451c4ddfe6.tar.gz yosys-80656ad17836a222f2359576d72f0b451c4ddfe6.tar.bz2 yosys-80656ad17836a222f2359576d72f0b451c4ddfe6.zip | |
Remove tests for now
| -rw-r--r-- | tests/various/logger_error.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_nowarning.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warn.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warning.ys | 6 |
4 files changed, 0 insertions, 24 deletions
diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys deleted file mode 100644 index 46fe7f506..000000000 --- a/tests/various/logger_error.ys +++ /dev/null @@ -1,6 +0,0 @@ -logger -werror "is implicitly declared." -expect error "is implicitly declared." 1 -read_verilog << EOF -module top(...); - assign b = w; -endmodule -EOF diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys deleted file mode 100644 index 87cbbc644..000000000 --- a/tests/various/logger_nowarning.ys +++ /dev/null @@ -1,6 +0,0 @@ -logger -expect-no-warnings -nowarn "is implicitly declared." -read_verilog << EOF -module top(...); - assign b = w; -endmodule -EOF diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys deleted file mode 100644 index 2316ae4c6..000000000 --- a/tests/various/logger_warn.ys +++ /dev/null @@ -1,6 +0,0 @@ -logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1 -read_verilog << EOF -module top(...); - assign b = w; -endmodule -EOF diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys deleted file mode 100644 index 642b1b97b..000000000 --- a/tests/various/logger_warning.ys +++ /dev/null @@ -1,6 +0,0 @@ -logger -expect warning "is implicitly declared." 2 -read_verilog << EOF -module top(...); - assign b = w; -endmodule -EOF |