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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:27:15 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:27:15 -0800 |
| commit | 6b58c1820c7bbacb4730af40e10592823b0eb15c (patch) | |
| tree | f878ff9902af732ca253999dcd596f6f987cc336 | |
| parent | 2e51dc1856aae456e15cafd484997bfbd102175e (diff) | |
| download | yosys-6b58c1820c7bbacb4730af40e10592823b0eb15c.tar.gz yosys-6b58c1820c7bbacb4730af40e10592823b0eb15c.tar.bz2 yosys-6b58c1820c7bbacb4730af40e10592823b0eb15c.zip | |
verilog: improve specify support when not in -specify mode
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 20 | ||||
| -rw-r--r-- | tests/various/specify.v | 2 | ||||
| -rw-r--r-- | tests/various/specify.ys | 2 |
3 files changed, 8 insertions, 16 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index f37c6d99b..155de8f90 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1043,7 +1043,7 @@ list_of_specparam_assignments: specparam_assignment | list_of_specparam_assignments ',' specparam_assignment; specparam_assignment: - ignspec_id '=' constant_mintypmax_expression ; + ignspec_id '=' ignspec_expr ; ignspec_opt_cond: TOK_IF '(' ignspec_expr ')' | /* empty */; @@ -1060,13 +1060,15 @@ simple_path_declaration : ; path_delay_value : - '(' path_delay_expression list_of_path_delay_extra_expressions ')' - | path_delay_expression - | path_delay_expression list_of_path_delay_extra_expressions + '(' ignspec_expr list_of_path_delay_extra_expressions ')' + | ignspec_expr + | ignspec_expr list_of_path_delay_extra_expressions ; list_of_path_delay_extra_expressions : - ',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions; + ',' ignspec_expr + | ',' ignspec_expr list_of_path_delay_extra_expressions + ; specify_edge_identifier : TOK_POSEDGE | TOK_NEGEDGE ; @@ -1120,14 +1122,6 @@ system_timing_args : system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg | system_timing_args ',' system_timing_arg ; -path_delay_expression : - ignspec_constant_expression; - -constant_mintypmax_expression : - ignspec_constant_expression - | ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression - ; - // for the time being this is OK, but we may write our own expr here. // as I'm not sure it is legal to use a full expr here (probably not) // On the other hand, other rules requiring constant expressions also use 'expr' diff --git a/tests/various/specify.v b/tests/various/specify.v index aa8aca4bc..5655ded21 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,11 +7,9 @@ module test ( if (EN) Q <= D; specify -`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); -`endif endspecify endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 00597e1e2..a2b6038e4 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,4 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v +read_verilog specify.v |