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Age
Files
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Update to .smv backend
Aman Goel
2018-10-01
2
-35
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+54
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Merge pull request #4 from YosysHQ/master
Aman Goel
2018-10-01
31
-107
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+529
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Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
Clifford Wolf
2018-09-30
1
-1
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+1
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Fix handling of $past 2nd argument in read_verilog
Clifford Wolf
2018-09-30
1
-1
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+1
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Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
Clifford Wolf
2018-09-28
1
-4
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+4
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Update to v2 YosysVS template
Clifford Wolf
2018-09-28
1
-4
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+4
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Add "read_verilog -noassert -noassume -assert-assumes"
Clifford Wolf
2018-09-24
3
-6
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+49
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Added support for ommited "parameter" in Verilog-2001 style parameter decl in...
Clifford Wolf
2018-09-23
1
-3
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+9
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Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc
Clifford Wolf
2018-09-23
1
-11
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+11
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added prefix to FDirection constants, fixing windows build
Miodrag Milanovic
2018-09-21
1
-11
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+11
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Update CHANGELOG
Clifford Wolf
2018-09-23
1
-2
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+35
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Update CHANGLELOG
Clifford Wolf
2018-09-21
1
-5
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+27
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Update Changelog
Clifford Wolf
2018-09-21
1
-1
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+54
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Merge pull request #633 from mmicko/master
Clifford Wolf
2018-09-19
3
-1
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+14
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Fix Cygwin build and document needed packages
Miodrag Milanovic
2018-09-19
3
-1
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+14
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Merge pull request #631 from acw1251/master
Clifford Wolf
2018-09-19
2
-5
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+5
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Fixed typo in "verilog_write" help message
acw1251
2018-09-18
2
-5
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+5
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Merge pull request #625 from aman-goel/master
Clifford Wolf
2018-09-14
1
-1
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+7
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Minor revision to -expose in setundef pass
Aman Goel
2018-09-10
1
-1
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+7
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Merge pull request #627 from acw1251/master
Clifford Wolf
2018-09-14
1
-1
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+1
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Fixed minor typo in "sim" help message
acw1251
2018-09-12
1
-1
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+1
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Add iCE40 SB_SPRAM256KA simulation model
Clifford Wolf
2018-09-10
1
-9
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+30
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Add $lut support to Verilog back-end
Clifford Wolf
2018-09-06
1
-0
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+13
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Add "verific -L <int>" option
Clifford Wolf
2018-09-04
3
-2
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+16
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Add "make ystests"
Clifford Wolf
2018-08-30
3
-0
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+10
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Add GCC to osx deps (#620)
Miodrag Milanović
2018-08-28
1
-1
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+1
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Merge pull request #619 from mmicko/master
Clifford Wolf
2018-08-28
2
-6
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+0
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Remove mercurial, since it is not needed anymore
Miodrag Milanovic
2018-08-28
2
-6
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+0
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Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes
Clifford Wolf
2018-08-28
1
-17
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+112
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Merge branch 'master' into firrtl+modules+shiftfixes
Jim Lawson
2018-08-27
12
-39
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+92
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Merge pull request #3 from YosysHQ/master
Jim Lawson
2018-08-27
12
-39
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+92
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Add "make coverage"
Clifford Wolf
2018-08-27
8
-13
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+21
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Add ENABLE_GCOV build option
Clifford Wolf
2018-08-27
1
-0
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+11
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Merge pull request #617 from mmicko/master
Clifford Wolf
2018-08-25
1
-1
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+1
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static link flag on main executable
Miodrag Milanovic
2018-08-25
1
-1
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+1
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Merge pull request #610 from udif/udif_specify_round2
Clifford Wolf
2018-08-23
1
-16
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+39
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Fixed all known specify/endspecify issues, without breaking 'make test'.
Udi Finkelstein
2018-08-20
1
-12
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+12
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Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...
Udi Finkelstein
2018-08-20
1
-10
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+22
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A few minor enhancements to specify block parsing.
Udi Finkelstein
2018-08-15
1
-2
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+13
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Merge pull request #614 from udif/pr_disable_dump_ptr
Clifford Wolf
2018-08-23
3
-9
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+20
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Added -no_dump_ptr flag for AST dump options in 'read_verilog'
Udi Finkelstein
2018-08-23
3
-9
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+20
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Remove unused functions.
Jim Lawson
2018-08-27
1
-10
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+0
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Add support for module instances.
Jim Lawson
2018-08-23
1
-17
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+122
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Merge pull request #1 from YosysHQ/master
Jim Lawson
2018-08-22
196
-770
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+2533
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Add "verific -work" help message
Clifford Wolf
2018-08-22
1
-0
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+7
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Add Verific -work parameter
Clifford Wolf
2018-08-22
1
-8
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+18
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Merge pull request #606 from cr1901/show-win
Clifford Wolf
2018-08-19
1
-3
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+20
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Update show pass documentation with Windows caveats.
William D. Jones
2018-08-15
1
-1
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+2
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Fix run_command() when using -format and -viewer in show pass.
William D. Jones
2018-08-15
1
-2
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+18
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Merge pull request #608 from mmicko/master
Clifford Wolf
2018-08-18
1
-1
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+19
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