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* Update to .smv backendAman Goel2018-10-012-35/+54
* Merge pull request #4 from YosysHQ/masterAman Goel2018-10-0131-107/+529
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| * Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-301-1/+1
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| | * Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
| * | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-281-4/+4
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| | * Update to v2 YosysVS templateClifford Wolf2018-09-281-4/+4
| * | Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
| * | Added support for ommited "parameter" in Verilog-2001 style parameter decl in...Clifford Wolf2018-09-231-3/+9
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| * Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rcClifford Wolf2018-09-231-11/+11
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| | * added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-09-211-11/+11
| * | Update CHANGELOGClifford Wolf2018-09-231-2/+35
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| * Update CHANGLELOGClifford Wolf2018-09-211-5/+27
| * Update ChangelogClifford Wolf2018-09-211-1/+54
| * Merge pull request #633 from mmicko/masterClifford Wolf2018-09-193-1/+14
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| | * Fix Cygwin build and document needed packagesMiodrag Milanovic2018-09-193-1/+14
| * | Merge pull request #631 from acw1251/masterClifford Wolf2018-09-192-5/+5
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| | * Fixed typo in "verilog_write" help messageacw12512018-09-182-5/+5
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| * Merge pull request #625 from aman-goel/masterClifford Wolf2018-09-141-1/+7
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* | Minor revision to -expose in setundef passAman Goel2018-09-101-1/+7
| * Merge pull request #627 from acw1251/masterClifford Wolf2018-09-141-1/+1
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| | * Fixed minor typo in "sim" help messageacw12512018-09-121-1/+1
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| * Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
| * Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
| * Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
| * Add "make ystests"Clifford Wolf2018-08-303-0/+10
| * Add GCC to osx deps (#620)Miodrag Milanović2018-08-281-1/+1
| * Merge pull request #619 from mmicko/masterClifford Wolf2018-08-282-6/+0
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| | * Remove mercurial, since it is not needed anymoreMiodrag Milanovic2018-08-282-6/+0
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| * Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixesClifford Wolf2018-08-281-17/+112
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| | * Merge branch 'master' into firrtl+modules+shiftfixesJim Lawson2018-08-2712-39/+92
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| | | * Merge pull request #3 from YosysHQ/masterJim Lawson2018-08-2712-39/+92
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| * | | Add "make coverage"Clifford Wolf2018-08-278-13/+21
| * | | Add ENABLE_GCOV build optionClifford Wolf2018-08-271-0/+11
| * | | Merge pull request #617 from mmicko/masterClifford Wolf2018-08-251-1/+1
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| | * | | static link flag on main executableMiodrag Milanovic2018-08-251-1/+1
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| * | | Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
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| | * | | Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | * | | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...Udi Finkelstein2018-08-201-10/+22
| | * | | A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| * | | | Merge pull request #614 from udif/pr_disable_dump_ptrClifford Wolf2018-08-233-9/+20
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| | * | | | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-233-9/+20
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| | | * | Remove unused functions.Jim Lawson2018-08-271-10/+0
| | | * | Add support for module instances.Jim Lawson2018-08-231-17/+122
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| | | * Merge pull request #1 from YosysHQ/masterJim Lawson2018-08-22196-770/+2533
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| * | | Add "verific -work" help messageClifford Wolf2018-08-221-0/+7
| * | | Add Verific -work parameterClifford Wolf2018-08-221-8/+18
| * | | Merge pull request #606 from cr1901/show-winClifford Wolf2018-08-191-3/+20
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| | * | | Update show pass documentation with Windows caveats.William D. Jones2018-08-151-1/+2
| | * | | Fix run_command() when using -format and -viewer in show pass.William D. Jones2018-08-151-2/+18
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| * | | Merge pull request #608 from mmicko/masterClifford Wolf2018-08-181-1/+19
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