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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-22 17:22:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-08-22 17:22:24 +0200 |
| commit | 408077769ff022f78f10ec1ffb60926361f8dc9f (patch) | |
| tree | 02b9412c9249cce3714972c8385d66f8093bfc17 | |
| parent | 4b02ee91627c49bd4ea0e89d6c8531283501a24b (diff) | |
| download | yosys-408077769ff022f78f10ec1ffb60926361f8dc9f.tar.gz yosys-408077769ff022f78f10ec1ffb60926361f8dc9f.tar.bz2 yosys-408077769ff022f78f10ec1ffb60926361f8dc9f.zip | |
Add "verific -work" help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verific/verific.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index cb31634dd..1dd6d7e24 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1706,11 +1706,18 @@ struct VerificPass : public Pass { log("\n"); log("Like -sv, but define FORMAL instead of SYNTHESIS.\n"); log("\n"); + log("\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n"); log("\n"); log("Load the specified VHDL files into Verific.\n"); log("\n"); log("\n"); + log(" verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n"); + log("\n"); + log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n"); + log("(default library when -work is not present: \"work\")\n"); + log("\n"); + log("\n"); log(" verific -vlog-incdir <directory>..\n"); log("\n"); log("Add Verilog include directories.\n"); |