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| author | Clifford Wolf <clifford@clifford.at> | 2018-09-14 12:34:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-09-14 12:34:51 +0200 |
| commit | 1936d4408e6a359644681ec0f1e0f62c368458b7 (patch) | |
| tree | 9ba51f4507ab80a32e2e710c3fb49eebe18cfe5b | |
| parent | 51f1bbeeb08020a9b739d2bd0cf4d79ca6e62015 (diff) | |
| parent | 5fe16c25b81d507fa41381eca70c5aada59db25f (diff) | |
| download | yosys-1936d4408e6a359644681ec0f1e0f62c368458b7.tar.gz yosys-1936d4408e6a359644681ec0f1e0f62c368458b7.tar.bz2 yosys-1936d4408e6a359644681ec0f1e0f62c368458b7.zip | |
Merge pull request #627 from acw1251/master
Fixed minor typo in "sim" help message
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index fadffcdbc..53e248adf 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -778,7 +778,7 @@ struct SimPass : public Pass { log(" number of cycles to simulate (default: 20)\n"); log("\n"); log(" -a\n"); - log(" include all nets in VCD output, nut just those with public names\n"); + log(" include all nets in VCD output, not just those with public names\n"); log("\n"); log(" -w\n"); log(" writeback mode: use final simulation state as new init state\n"); |