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* Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
* add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
* Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1615-47/+913
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| * ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| * Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-143-0/+136
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| | * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-133-0/+136
| * | Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streamsClifford Wolf2019-11-141-6/+286
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| | * \ Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python...Benedikt Tutzer2019-10-1525-61/+345
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| | * | | Fix renaming all classes to Cpp*Benedikt Tutzer2019-10-091-2/+2
| | * | | Expose global variables and allow logging to python streamsBenedikt Tutzer2019-10-091-6/+286
| * | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
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| | * | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | * | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| * | | | | Merge branch 'makaimann-label-bads-btor'Clifford Wolf2019-11-141-1/+6
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| | * | | | | Use cell name for btor bad state props when it is a public nameClifford Wolf2019-11-141-9/+5
| | * | | | | Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into mak...Clifford Wolf2019-11-141-1/+10
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| | * | | | | Add an info string symbol for bad states in btor backendMakai Mann2019-11-111-1/+10
| * | | | | | Merge pull request #1488 from whitequark/flowmap-fixeswhitequark2019-11-131-2/+3
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| | * | | | | flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| | * | | | | flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
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| * | | | | Merge pull request #1486 from YosysHQ/clifford/fsmdetectfixClifford Wolf2019-11-131-6/+10
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| | * | | | | Update fsm_detect bugfixClifford Wolf2019-11-121-3/+4
| | * | | | | Bugfix in fsm_detectClifford Wolf2019-11-121-6/+9
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| * | | | | Merge pull request #1484 from YosysHQ/clifford/cmp2luteqneClifford Wolf2019-11-126-18/+35
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| | * | | | Fixed testsMiodrag Milanovic2019-11-115-17/+34
| | * | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
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* | | | | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-112-4/+15
* | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1129-23010/+30701
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| * | | | Merge pull request #1470 from YosysHQ/clifford/subpassdocClifford Wolf2019-11-101-0/+46
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| | * | | | Add CodingReadme section on script passesClifford Wolf2019-10-311-0/+46
| * | | | | Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| * | | | | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| * | | | | Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
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| * | | | Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
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| | * | | | write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
| * | | | | Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
| * | | | | Merge pull request #1455 from YosysHQ/dave/ultrascaleplusDavid Shah2019-10-249-417/+1153
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| | * | | | | xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| | * | | | | xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| * | | | | | Add "verific -L"Clifford Wolf2019-10-241-1/+12
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| * | | | | Bugfix in smtio vcd handling of $-identifiersClifford Wolf2019-10-231-6/+9
| * | | | | xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| * | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
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| | * | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
| * | | | | | Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
| * | | | | | Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
* | | | | | | fix wide lutsPepijn de Vos2019-11-062-19/+22
* | | | | | | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
* | | | | | | add IOBUFPepijn de Vos2019-10-282-1/+10
* | | | | | | add tristate buffer and testPepijn de Vos2019-10-283-2/+21
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