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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-12 17:31:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-11-12 17:31:30 +0100 |
| commit | 4be5a0fd7c1573f81c6c70a16601f7ce5ab87210 (patch) | |
| tree | 3f4f2ea5b501233b2d97d8b7b5491fa69ececb56 | |
| parent | 16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856 (diff) | |
| download | yosys-4be5a0fd7c1573f81c6c70a16601f7ce5ab87210.tar.gz yosys-4be5a0fd7c1573f81c6c70a16601f7ce5ab87210.tar.bz2 yosys-4be5a0fd7c1573f81c6c70a16601f7ce5ab87210.zip | |
Update fsm_detect bugfix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 61e6f8011..fb3896669 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -173,9 +173,10 @@ static void detect_fsm(RTLIL::Wire *wire) if (set_output || clr_output) { for (auto &port_it : cell->connections()) - for (auto bit : assign_map(port_it.second)) - if (bit.wire != nullptr && !sig_q_bits.count(bit)) - goto next_cellport; + if (cell->input(port_it.first)) + for (auto bit : assign_map(port_it.second)) + if (bit.wire != nullptr && !sig_q_bits.count(bit)) + goto next_cellport; } if (set_output || clr_output) { |