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authorClifford Wolf <clifford@clifford.at>2019-11-13 12:34:27 +0100
committerGitHub <noreply@github.com>2019-11-13 12:34:27 +0100
commit6e332161dbdc399c41041cebaf83cbb156b331a7 (patch)
tree3f4f2ea5b501233b2d97d8b7b5491fa69ececb56
parente0ba78bdf2d65ace45be575de6a1cc43baae7f22 (diff)
parent4be5a0fd7c1573f81c6c70a16601f7ce5ab87210 (diff)
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Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
Bugfix in fsm_detect
-rw-r--r--passes/fsm/fsm_detect.cc16
1 files changed, 10 insertions, 6 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 5ae991b28..fb3896669 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -158,22 +158,25 @@ static void detect_fsm(RTLIL::Wire *wire)
std::set<sig2driver_entry_t> cellport_list;
sig2user.find(sig_q, cellport_list);
+ auto sig_q_bits = sig_q.to_sigbit_pool();
+
for (auto &cellport : cellport_list)
{
RTLIL::Cell *cell = cellport.first;
bool set_output = false, clr_output = false;
- if (cell->type == "$ne")
+ if (cell->type.in("$ne", "$reduce_or", "$reduce_bool"))
set_output = true;
- if (cell->type == "$eq")
+ if (cell->type.in("$eq", "$logic_not", "$reduce_and"))
clr_output = true;
- if (!set_output && !clr_output) {
- clr_output = true;
+ if (set_output || clr_output) {
for (auto &port_it : cell->connections())
- if (port_it.first != "\\A" || port_it.first != "\\Y")
- clr_output = false;
+ if (cell->input(port_it.first))
+ for (auto bit : assign_map(port_it.second))
+ if (bit.wire != nullptr && !sig_q_bits.count(bit))
+ goto next_cellport;
}
if (set_output || clr_output) {
@@ -184,6 +187,7 @@ static void detect_fsm(RTLIL::Wire *wire)
ce.set(sig, val);
}
}
+ next_cellport:;
}
SigSpec sig_y = sig_d, sig_undef;