| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Progress in "share" pass | Clifford Wolf | 2014-07-20 | 1 | -112/+185 |
| * | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 | 2 | -3/+11 |
| * | Added SIZE() macro | Clifford Wolf | 2014-07-20 | 1 | -0/+2 |
| * | Added log_cell() | Clifford Wolf | 2014-07-20 | 2 | -0/+17 |
| * | Progress in "share" pass | Clifford Wolf | 2014-07-20 | 1 | -19/+56 |
| * | Added tests/vloghtb | Clifford Wolf | 2014-07-20 | 2 | -0/+18 |
| * | Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b... | Clifford Wolf | 2014-07-20 | 1 | -17/+21 |
| * | Added support for $bu0 to verilog backend | Clifford Wolf | 2014-07-20 | 1 | -0/+16 |
| * | Started to implement real resource sharing | Clifford Wolf | 2014-07-19 | 2 | -0/+444 |
| * | Fixed log_id() memory corruption | Clifford Wolf | 2014-07-19 | 2 | -5/+10 |
| * | Improved memory_share log messages | Clifford Wolf | 2014-07-19 | 1 | -3/+3 |
| * | More verbose memory_share help message | Clifford Wolf | 2014-07-19 | 1 | -0/+17 |
| * | Added SAT-based write-port sharing to memory_share | Clifford Wolf | 2014-07-19 | 2 | -0/+205 |
| * | Added ModWalker helper class | Clifford Wolf | 2014-07-19 | 1 | -0/+298 |
| * | Some "const" cleanups in SigMap | Clifford Wolf | 2014-07-19 | 1 | -4/+4 |
| * | Fixed bug in memory_share feedback-to-en code | Clifford Wolf | 2014-07-19 | 2 | -4/+36 |
| * | Added translation from read-feedback to en-signals in memory_share | Clifford Wolf | 2014-07-18 | 3 | -10/+264 |
| * | Improved seeding of color rng in show command | Clifford Wolf | 2014-07-18 | 1 | -1/+3 |
| * | Only create collision detect logic in memory_share if necessary | Clifford Wolf | 2014-07-18 | 1 | -4/+47 |
| * | Bugfix in tests/memories/run-test.sh | Clifford Wolf | 2014-07-18 | 1 | -2/+2 |
| * | added tests/memories | Clifford Wolf | 2014-07-18 | 5 | -0/+133 |
| * | Added memory_share | Clifford Wolf | 2014-07-18 | 3 | -0/+266 |
| * | Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> | Clifford Wolf | 2014-07-18 | 1 | -0/+1 |
| * | Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port | Clifford Wolf | 2014-07-18 | 1 | -0/+15 |
| * | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 | 2 | -73/+158 |
| * | Added log_id() helper function | Clifford Wolf | 2014-07-18 | 1 | -0/+8 |
| * | Also simulate unmapped memories in "make test" | Clifford Wolf | 2014-07-17 | 1 | -1/+1 |
| * | Implemented dynamic bit-/part-select for memory writes | Clifford Wolf | 2014-07-17 | 2 | -3/+66 |
| * | Fixed simlib.v model for $mem | Clifford Wolf | 2014-07-17 | 1 | -15/+15 |
| * | Added support for bit/part select to mem2reg rewriter | Clifford Wolf | 2014-07-17 | 2 | -0/+30 |
| * | Added support for constant bit- or part-select for memory writes | Clifford Wolf | 2014-07-17 | 2 | -9/+56 |
| * | Improved opt_reduce handling of mem wr_en mux bits | Clifford Wolf | 2014-07-17 | 1 | -5/+18 |
| * | Fixed RTLIL::SigSpec::append_bit() for appending constants | Clifford Wolf | 2014-07-17 | 1 | -2/+3 |
| * | Added support for "blackbox" attribute to iopadmap | Clifford Wolf | 2014-07-17 | 1 | -1/+1 |
| * | Added support for "blackbox" attribute to flatten/techmap | Clifford Wolf | 2014-07-17 | 1 | -1/+4 |
| * | Added "inout" ports support to read_liberty | Clifford Wolf | 2014-07-16 | 1 | -1/+6 |
| * | Set blackbox attribute in "read_liberty -lib" | Clifford Wolf | 2014-07-16 | 1 | -0/+3 |
| * | Fixed spelling of "direction" in read_liberty messages | Clifford Wolf | 2014-07-16 | 1 | -2/+2 |
| * | Merged new $mem/$memwr WR_EN interface | Clifford Wolf | 2014-07-16 | 10 | -82/+216 |
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| | * | Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface | Clifford Wolf | 2014-07-16 | 1 | -2/+13 |
| | * | improved opt_reduce for $mem/$memwr WR_EN multiplexers | Clifford Wolf | 2014-07-16 | 1 | -0/+80 |
| | * | changes in verilog frontend for new $mem/$memwr WR_EN interface | Clifford Wolf | 2014-07-16 | 2 | -7/+6 |
| | * | Changes to "memory" pass for new $memwr/$mem WR_EN interface | Clifford Wolf | 2014-07-16 | 3 | -38/+56 |
| | * | Updated simlib to new $mem/$memwr interface | Clifford Wolf | 2014-07-16 | 1 | -30/+55 |
| | * | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 | 2 | -5/+6 |
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| * | Added note to "make test": use git checkout of iverilog | Clifford Wolf | 2014-07-16 | 5 | -5/+15 |
| * | Added passing of various options to vhdl2verilog | Clifford Wolf | 2014-07-12 | 1 | -5/+36 |
| * | Use "verilog -sv" to parse .sv files | Clifford Wolf | 2014-07-11 | 1 | -0/+2 |
| * | Fixed processing of initial values for block-local variables | Clifford Wolf | 2014-07-11 | 1 | -0/+5 |
| * | now ignore init attributes on non-register wires in sat command | Clifford Wolf | 2014-07-05 | 3 | -4/+43 |
