| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | * | | | | | | Add log_checkpoint function and use it in opt_muxtree | Clifford Wolf | 2019-07-15 | 3 | -0/+9 | |
| | | * | | | | | | Fix first divergence in #1178 | Eddie Hung | 2019-07-09 | 1 | -1/+5 | |
| | * | | | | | | | Merge pull request #1189 from YosysHQ/eddie/fix1151 | Clifford Wolf | 2019-07-15 | 1 | -0/+4 | |
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| | | * | | | | | | | Error out if enable > dbits | Eddie Hung | 2019-07-13 | 1 | -0/+4 | |
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| | * | | | | | | | Merge pull request #1190 from YosysHQ/eddie/fix_1099 | Clifford Wolf | 2019-07-15 | 1 | -4/+8 | |
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| | | * | | | | | | | If ConstEval fails do not log_abort() but return gracefully | Eddie Hung | 2019-07-13 | 1 | -4/+8 | |
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| | * | | | | | | | Merge pull request #1191 from whitequark/opt_lut-log_debug | Clifford Wolf | 2019-07-15 | 1 | -56/+38 | |
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| | | * | | | | | | | opt_lut: make less chatty. | whitequark | 2019-07-13 | 1 | -56/+38 | |
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| | * | | | | | | | Merge pull request #1195 from Roman-Parise/master | Clifford Wolf | 2019-07-15 | 1 | -1/+1 | |
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| | | * | | | | | | | Updated FreeBSD dependencies in README.md | Roman-Parise | 2019-07-14 | 1 | -1/+1 | |
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| | * | | | | | | | Merge pull request #1197 from nakengelhardt/handle-setrlimit-fail | Clifford Wolf | 2019-07-15 | 1 | -1/+5 | |
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| | | * | | | | | | smt: handle failure of setrlimit syscall | N. Engelhardt | 2019-07-15 | 1 | -1/+5 | |
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| * | | | | | | | ice40_dsp to accept $__MUL16X16 too | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
| * | | | | | | | synth_ice40 to decompose into 16x16 | Eddie Hung | 2019-07-18 | 1 | -1/+3 | |
| * | | | | | | | mul2dsp to create cells that can be interchanged with $mul | Eddie Hung | 2019-07-18 | 1 | -1/+7 | |
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| * | | | | | | Check if RHS is empty first | Eddie Hung | 2019-07-18 | 1 | -0/+2 | |
| * | | | | | | Make consistent | Eddie Hung | 2019-07-18 | 1 | -1/+2 | |
| * | | | | | | Do not autoremove ffP aor muxP | Eddie Hung | 2019-07-18 | 1 | -2/+0 | |
| * | | | | | | Improve pattern matcher to match subsets of $dffe? cells | Eddie Hung | 2019-07-18 | 2 | -12/+22 | |
| * | | | | | | Improve A/B reg packing | Eddie Hung | 2019-07-18 | 2 | -6/+11 | |
| * | | | | | | Do not autoremove A/B registers since they might have other consumers | Eddie Hung | 2019-07-18 | 1 | -2/+0 | |
| * | | | | | | Fix xilinx_dsp index cast | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| * | | | | | | Fix signed multiplier decomposition | Eddie Hung | 2019-07-18 | 1 | -29/+36 | |
| * | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
| * | | | | | | Working for unsigned | Eddie Hung | 2019-07-18 | 1 | -52/+28 | |
| * | | | | | | Cleanup | Eddie Hung | 2019-07-18 | 1 | -70/+58 | |
| * | | | | | | Wrong wildcard symbol | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
| * | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-18 | 1 | -31/+41 | |
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| | * | | | | | | mul2dsp: Lower partial products always have unsigned inputs | David Shah | 2019-07-18 | 1 | -31/+41 | |
| * | | | | | | | Make all operands signed | Eddie Hung | 2019-07-17 | 1 | -1/+1 | |
| * | | | | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 | |
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| * | | | | | | Pattern matcher to check pool of bits, not exactly | Eddie Hung | 2019-07-17 | 2 | -5/+11 | |
| * | | | | | | Fix mul2dsp signedness | Eddie Hung | 2019-07-17 | 1 | -42/+38 | |
| * | | | | | | A_SIGNED == B_SIGNED so flip both | Eddie Hung | 2019-07-17 | 1 | -21/+12 | |
| * | | | | | | SigSpec::remove_const() to return SigSpec& | Eddie Hung | 2019-07-17 | 2 | -2/+3 | |
| * | | | | | | Add DSP_{A,B}_SIGNEDONLY macro | Eddie Hung | 2019-07-16 | 1 | -11/+40 | |
| * | | | | | | Signedness | Eddie Hung | 2019-07-16 | 2 | -8/+8 | |
| * | | | | | | Signed extension | Eddie Hung | 2019-07-16 | 2 | -6/+6 | |
| * | | | | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 2 | -4/+4 | |
| * | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 4 | -27/+35 | |
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| | * | | | | | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 | |
| | * | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si... | David Shah | 2019-07-16 | 2 | -4/+8 | |
| | * | | | | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH | David Shah | 2019-07-16 | 1 | -18/+22 | |
| | * | | | | | | mul2dsp: Fix indentation | David Shah | 2019-07-16 | 1 | -7/+7 | |
| * | | | | | | | Add support {A,B,P}REG packing | Eddie Hung | 2019-07-16 | 2 | -55/+94 | |
| * | | | | | | | SigSpec::extract to allow negative length | Eddie Hung | 2019-07-16 | 1 | -1/+1 | |
| * | | | | | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 | |
| * | | | | | | | Do not swap if equals | Eddie Hung | 2019-07-15 | 1 | -1/+1 | |
| * | | | | | | | SigSpec::extend_u0() to return *this | Eddie Hung | 2019-07-15 | 2 | -2/+3 | |
| * | | | | | | | Oops forgot these files | Eddie Hung | 2019-07-15 | 3 | -2/+12 | |
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index : iCE40/yosys | |
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