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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-09 15:49:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-09 15:49:16 -0700 |
| commit | 1122a2e0671ed00b7c03658f5012e34df12f26de (patch) | |
| tree | 4a74545d5a029890d2db899e3bd9c89860338a59 | |
| parent | 27b27b8781ab8d57aa85a432aba7e914570feffb (diff) | |
| download | yosys-1122a2e0671ed00b7c03658f5012e34df12f26de.tar.gz yosys-1122a2e0671ed00b7c03658f5012e34df12f26de.tar.bz2 yosys-1122a2e0671ed00b7c03658f5012e34df12f26de.zip | |
Fix first divergence in #1178
| -rw-r--r-- | passes/opt/wreduce.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 1fbc41082..65068238b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -430,6 +430,7 @@ struct WreduceWorker for (auto w : module->wires()) complete_wires.insert(mi.sigmap(w)); + std::vector<std::pair<Wire*,Wire*>> swap_wire_names; for (auto w : module->selected_wires()) { int unused_top_bits = 0; @@ -454,9 +455,12 @@ struct WreduceWorker log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits); module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); - module->swap_names(w, nw); + swap_wire_names.emplace_back(w, nw); } + for (const auto &i : swap_wire_names) + module->swap_names(i.first, i.second); + if (!remove_init_bits.empty()) { for (auto w : module->wires()) { if (w->attributes.count("\\init")) { |