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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:21:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:21:23 -0700 |
| commit | e22a7522422ec5f2f6db52d4e9c98d09868ea3e3 (patch) | |
| tree | a952f37650e42c3eebc17a5ce92a33b0770763ef | |
| parent | 90ac147eb2139dacc18f80515984ef83d7acb6a1 (diff) | |
| download | yosys-e22a7522422ec5f2f6db52d4e9c98d09868ea3e3.tar.gz yosys-e22a7522422ec5f2f6db52d4e9c98d09868ea3e3.tar.bz2 yosys-e22a7522422ec5f2f6db52d4e9c98d09868ea3e3.zip | |
Make consistent
| -rw-r--r-- | techlibs/common/mul2dsp.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 2819c939e..ee53701ee 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -201,7 +201,8 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
.Y(partial[n-1])
);
- assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
+ assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
+ assign Y = partial_sum[n-1];
end
else begin
if (A_SIGNED)
|