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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:06:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:06:07 -0700 |
| commit | d086dfb5b0d4f1f8e60a9e32d874a1f94cf73c66 (patch) | |
| tree | ad4e52c436a9b90ec6787ad910347cc037277331 | |
| parent | 5d1ce043812b9b86ee3c3588c430ea1cd57fee1e (diff) | |
| download | yosys-d086dfb5b0d4f1f8e60a9e32d874a1f94cf73c66.tar.gz yosys-d086dfb5b0d4f1f8e60a9e32d874a1f94cf73c66.tar.bz2 yosys-d086dfb5b0d4f1f8e60a9e32d874a1f94cf73c66.zip | |
SigSpec::extract to allow negative length
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ebb6f5bf6..6f5082138 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,7 +3353,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length); + return std::vector<RTLIL::SigBit>(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) |