aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
| * | | | | | | | | Improve igloo2 exmapleClifford Wolf2019-03-054-8/+16
| * | | | | | | | | Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
| |\ \ \ \ \ \ \ \ \
| | * | | | | | | | | Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | * | | | | | | | | Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | * | | | | | | | | Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-012-26/+19
| | * | | | | | | | | Modify arguments to match existing style.Keith Rothman2019-03-012-11/+11
| | * | | | | | | | | Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0112-227/+600
| * | | | | | | | | | Merge pull request #850 from daveshah1/ecp5_warn_conflictClifford Wolf2019-03-051-2/+7
| |\ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | ecp5: Demote conflicting FF init values to a warningDavid Shah2019-03-041-2/+7
| * | | | | | | | | | | Add missing newlineClifford Wolf2019-03-051-1/+1
| * | | | | | | | | | | Merge pull request #851 from kprasadvnsi/masterClifford Wolf2019-03-057-0/+55
| |\ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | Added examples/anlogic/Kali Prasad2019-03-047-0/+55
| * | | | | | | | | | | | Merge pull request #852 from ucb-bar/firrtlfixesClifford Wolf2019-03-052-2/+2
| |\ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-042-2/+2
| | |/ / / / / / / / / / /
| * / / / / / / / / / / / Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
| |/ / / / / / / / / / /
| * | | | | | | | | | | Improve igloo2 exampleClifford Wolf2019-03-032-3/+10
| * | | | | | | | | | | Update igloo2 example to Libero v12.0Clifford Wolf2019-03-032-6/+5
| * | | | | | | | | | | Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
| |\ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
| * | | | | | | | | | | | Merge pull request #849 from YosysHQ/clifford/dynportsClifford Wolf2019-03-024-1/+24
| |\ \ \ \ \ \ \ \ \ \ \ \ | | |/ / / / / / / / / / / | |/| | | | | | | | | | |
| | * | | | | | | | | | | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-024-1/+24
| |/ / / / / / / / / / /
| * | | | | | | | | | | Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| * | | | | | | | | | | Merge pull request #847 from YosysHQ/clifford/fix785Clifford Wolf2019-03-021-0/+35
| |\ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
| |/ / / / / / / / / / /
| * | | | | | | | | | | Merge pull request #843 from YosysHQ/clifford/mem2regconstidxClifford Wolf2019-03-022-0/+13
| |\ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
| * | | | | | | | | | | | Merge pull request #845 from YosysHQ/clifford/travisnomacosClifford Wolf2019-03-021-5/+5
| |\ \ \ \ \ \ \ \ \ \ \ \ | | |_|/ / / / / / / / / / | |/| | | | | | | | | | |
| | * | | | | | | | | | | Disable macOS builds in TravisClifford Wolf2019-03-021-5/+5
| |/ / / / / / / / / / /
| * | | | | | | | | | | Try again for passes/pmgen/ice40_dsp_pm.h ruleLarry Doolittle2019-03-012-8/+9
| * | | | | | | | | | | Minor improvements in READMEClifford Wolf2019-03-011-3/+16
| |/ / / / / / / / / /
| * / / / / / / / / / Fix "write_edif -gndvccy"Clifford Wolf2019-03-011-1/+1
| |/ / / / / / / / /
| * | | | | | | | | Merge pull request #841 from mmicko/masterClifford Wolf2019-03-011-2/+3
| |\ \ \ \ \ \ \ \ \
| | * | | | | | | | | Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
| |/ / / / / / / / /
| * | | | | | | | | Improve "read" error msgClifford Wolf2019-02-281-1/+1
| * | | | | | | | | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
| |\ \ \ \ \ \ \ \ \
| | * | | | | | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| * | | | | | | | | | Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| * | | | | | | | | | Merge pull request #837 from YosysHQ/clifford/fix835Clifford Wolf2019-02-281-5/+24
| |\ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | Fix multiple issues in wreduce FF handling, fixes #835Clifford Wolf2019-02-281-5/+24
| |/ / / / / / / / / /
| * | | | | | | | | | Merge pull request #834 from YosysHQ/clifford/siminitClifford Wolf2019-02-282-3/+12
| |\ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | Add "write_verilog -siminit"Clifford Wolf2019-02-282-3/+12
| |/ / / / / / / / / /
| * | | | | | | | | | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-289-29/+29
| * | | | | | | | | | Fix pmgen for in-tree buildsClifford Wolf2019-02-282-8/+9
| * | | | | | | | | | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
| |\ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | * | | | | | | | | | ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | * | | | | | | | | | ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | * | | | | | | | | | ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | * | | | | | | | | | ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | * | | | | | | | | | ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 07:39:56 +0000