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author | Elms <elms@freshred.net> | 2019-02-28 16:22:24 -0800 |
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committer | Elms <elms@freshred.net> | 2019-02-28 16:23:40 -0800 |
commit | cd2902ab1fec57503320e32ba5620c6487f9cb85 (patch) | |
tree | 7c9fbaa295a60c551449348f2c9c3acfcca85282 | |
parent | 64d91219b4e81366976a0e0a9b28efa4bd825022 (diff) | |
download | yosys-cd2902ab1fec57503320e32ba5620c6487f9cb85.tar.gz yosys-cd2902ab1fec57503320e32ba5620c6487f9cb85.tar.bz2 yosys-cd2902ab1fec57503320e32ba5620c6487f9cb85.zip |
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
-rw-r--r-- | techlibs/ice40/brams_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index 19a61d73b..ad3bccd21 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -7,8 +7,8 @@ module \$__ICE40_RAM4K ( input [10:0] WADDR, input [15:0] MASK, WDATA ); - parameter integer READ_MODE = 0; - parameter integer WRITE_MODE = 0; + parameter [1:0] READ_MODE = 0; + parameter [1:0] WRITE_MODE = 0; parameter [0:0] NEGCLK_R = 0; parameter [0:0] NEGCLK_W = 0; |