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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-28 14:56:55 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-28 15:03:03 -0800 |
| commit | 241901461ae02c6a41837e254088f277b8167476 (patch) | |
| tree | 125c3b702ca30880f6639395ed024d5eac77b2b3 | |
| parent | e2fc18f27b5e9f506724a486787c2106b9f7fb4f (diff) | |
| download | yosys-241901461ae02c6a41837e254088f277b8167476.tar.gz yosys-241901461ae02c6a41837e254088f277b8167476.tar.bz2 yosys-241901461ae02c6a41837e254088f277b8167476.zip | |
Add "write_verilog -siminit"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 13 | ||||
| -rwxr-xr-x | tests/tools/autotest.sh | 2 |
2 files changed, 12 insertions, 3 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d351a6266..6818edb7a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -33,7 +33,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal; +bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit; int auto_name_counter, auto_name_offset, auto_name_digits; std::map<RTLIL::IdString, int> auto_name_map; std::set<RTLIL::IdString> reg_wires, reg_ct; @@ -1310,7 +1310,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } - if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { std::stringstream ss; dump_reg_init(ss, cell->getPort("\\Q")); if (!ss.str().empty()) { @@ -1607,6 +1607,10 @@ struct VerilogBackend : public Backend { log(" without this option all internal cells are converted to Verilog\n"); log(" expressions.\n"); log("\n"); + log(" -siminit\n"); + log(" add initial statements with hierarchical refs to initialize FFs when\n"); + log(" in -noexpr mode.\n"); + log("\n"); log(" -nodec\n"); log(" 32-bit constant values are by default dumped as decimal numbers,\n"); log(" not bit pattern. This option deactivates this feature and instead\n"); @@ -1663,6 +1667,7 @@ struct VerilogBackend : public Backend { nostr = false; defparam = false; decimal = false; + siminit = false; auto_prefix = ""; bool blackboxes = false; @@ -1739,6 +1744,10 @@ struct VerilogBackend : public Backend { decimal = true; continue; } + if (arg == "-siminit") { + siminit = true; + continue; + } if (arg == "-blackboxes") { blackboxes = true; continue; diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 99ec3e7cd..0b9aceacc 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -8,7 +8,7 @@ verbose=false keeprunning=false makejmode=false frontend="verilog" -backend_opts="-noattr -noexpr" +backend_opts="-noattr -noexpr -siminit" autotb_opts="" include_opts="" xinclude_opts="" |