aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Bump versionYosys Bot2021-02-161-1/+1
|
* Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
|\ | | | | Accept disable case for SVA liveness properties.
| * Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
| |
* | Bump versionYosys Bot2021-02-131-1/+1
| |
* | Merge pull request #2585 from YosysHQ/dave/nexus-dotproductgatecat2021-02-121-0/+115
|\ \ | | | | | | nexus: Add MULTADDSUB9X9WIDE sim model
| * | nexus: Add MULTADDSUB9X9WIDE sim modelDavid Shah2020-12-081-0/+115
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
| | |
* | | Bump versionYosys Bot2021-02-121-1/+1
| | |
* | | Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-114-72/+176
|\ \ \ | | | | | | | | verilog: refactored constant function evaluation
| * | | verilog: refactored constant function evaluationZachary Snow2021-02-044-72/+176
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* | | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-113-4/+29
|\ \ \ | | | | | | | | verlog: allow shadowing module ports within generate blocks
| * | | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-073-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | | | Merge pull request #2584 from antmicro/atom_type_signednessZachary Snow2021-02-112-4/+23
|\ \ \ \ | |/ / / |/| | | verilog_parser: fix missing is_signed attribute in type_atom
| * | | Add missing is_signed to type_atomKamil Rakoczy2021-02-112-4/+23
|/ / / | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | Bump versionYosys Bot2021-02-071-1/+1
| | |
* | | Merge pull request #2576 from zachjs/port-bind-sign-uniopwhitequark2021-02-063-8/+33
|\ \ \ | | | | | | | | genrtlil: fix signed port connection codegen failures
| * | | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-053-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* | | | Bump versionYosys Bot2021-02-061-1/+1
|/ / /
* | | Merge pull request #2572 from antmicro/check-labelswhitequark2021-02-052-0/+28
|\ \ \ | | | | | | | | verilog_parser: add label check to gen_block
| * | | Add check of begin/end labels for genblockKamil Rakoczy2021-02-042-0/+28
| |/ / | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* / / Bump versionYosys Bot2021-02-051-1/+1
|/ /
* | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-0433-258/+779
|\ \ | | | | | | verilog: significant block scoping improvements
| * | verilog: significant block scoping improvementsZachary Snow2021-01-3133-258/+779
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | | Bump versionYosys Bot2021-02-041-1/+1
| | |
* | | Merge pull request #2436 from dalance/fix_generatewhitequark2021-02-032-7/+4
|\ \ \ | | | | | | | | Fix begin/end in generate
| * | | Fix begin/end in generatedalance2020-11-112-7/+4
| | | |
* | | | Bump versionYosys Bot2021-01-311-1/+1
| | | |
* | | | Require latest Verific buildMiodrag Milanovic2021-01-301-1/+1
| | | |
* | | | Bump versionYosys Bot2021-01-301-1/+1
| | | |
* | | | ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case.
* | | | Merge pull request #2564 from whitequark/flatten-improve-errorwhitequark2021-01-291-1/+1
|\ \ \ \ | | | | | | | | | | flatten: clarify confusing error message
| * | | | flatten: clarify confusing error message.whitequark2021-01-261-1/+1
| | | | |
* | | | | Bump versionYosys Bot2021-01-291-1/+1
| | | | |
* | | | | Merge pull request #2569 from zachjs/macro-arg-surrounding-spaceswhitequark2021-01-282-1/+25
|\ \ \ \ \ | | | | | | | | | | | | verilog: strip leading and trailing spaces in macro args
| * | | | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-282-1/+25
| | |_|/ / | |/| | |
* | | | | Merge pull request #2535 from Ravenslofty/scc-specifyClaire Xen2021-01-282-18/+61
|\ \ \ \ \ | |/ / / / |/| | | | scc: Add -specify option to find loops in boxes
| * | | | scc: Add -specify option to find loops in boxesDan Ravensloft2021-01-262-18/+61
| | | | |
* | | | | Bump versionYosys Bot2021-01-271-1/+1
| | | | |
* | | | | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-273-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* | | | | xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
| | | | |
* | | | | Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
|\ \ \ \ \ | | | | | | | | | | | | cxxrtl: do not use `->template` for non-dependent names
| * | | | | cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
| | |/ / / | |/| | | | | | | | | | | | | This breaks build on MSVC but not GCC/Clang.
* | | | | Merge pull request #2544 from modwizcode/fix-clockwhitequark2021-01-261-7/+15
|\ \ \ \ \ | |/ / / / |/| | | | CXXRTL: Fix sliced bits as clock inputs
| * | | | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
| | | | |
| * | | | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
| | | | |
* | | | | Bump versionYosys Bot2021-01-261-1/+1
| | | | |
* | | | | Merge pull request #2549 from pgadfort/support-multiple-libswhitequark2021-01-251-15/+21
|\ \ \ \ \ | | | | | | | | | | | | adding support for passing multiple liberty files to abc
| * | | | | adding support for passing multiple liberty files to abcPeter Gadfort2021-01-181-15/+21
| | | | | |
* | | | | | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-252-1/+28
|\ \ \ \ \ \ | | | | | | | | | | | | | | verilog: allow spaces in macro arguments
| * | | | | | verilog: allow spaces in macro argumentsZachary Snow2021-01-202-1/+28
| |/ / / / /
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 22:01:45 +0000