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* Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
* Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
* Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
* OopsEddie Hung2019-10-041-1/+1
* Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
* Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
* Update ABC to git rev 623b5e8Clifford Wolf2019-10-031-1/+1
* Bump versionClifford Wolf2019-10-031-1/+1
* Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
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| * Fix for svinterfacesEddie Hung2019-09-301-2/+8
| * module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
* | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-032-6/+50
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| * | Add quick testEddie Hung2019-09-301-0/+10
| * | Add -select option to aigmapEddie Hung2019-09-301-6/+40
* | | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-032-27/+56
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| * | | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| * | | Add "check -mapped"Clifford Wolf2019-10-022-21/+36
* | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16David Shah2019-10-036-2/+184
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| * | | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| * | | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
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* | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wireEddie Hung2019-10-022-0/+32
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| * | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
| * | | | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
| * | | | Add testEddie Hung2019-09-301-0/+16
| * | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* | | | log_dump() to support State enumEddie Hung2019-10-023-0/+6
* | | | Merge pull request #1428 from YosysHQ/clifford/fixbtorClifford Wolf2019-10-021-6/+9
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| * | | Fix btor back-end to use "state" instead of "input" for undef init bitsClifford Wolf2019-10-021-6/+9
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* | | Merge pull request #1426 from YosysHQ/mmicko/fix_environMiodrag Milanović2019-10-011-0/+2
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| * | Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
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* / Fix typoEddie Hung2019-09-301-1/+1
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* Update doc for equiv_optEddie Hung2019-09-301-2/+3
* Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-3011-0/+1767
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| * rpc: new frontend.whitequark2019-09-309-0/+744
| * libs: import json11.whitequark2019-09-303-0/+1023
* | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructorsEddie Hung2019-09-301-0/+2
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| * | Generate Python wrappers for inline constructorsBenedikt Tutzer2019-09-231-0/+2
* | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-304-6/+10
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| * | | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
| * | | Open aig frontend as binary fileMiodrag Milanovic2019-09-294-5/+5
* | | | Bump versionClifford Wolf2019-09-301-1/+1
* | | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2syncClifford Wolf2019-09-301-0/+2
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| * | | | equiv_opt to call async2sync when not -multiclock like SymbiYosysEddie Hung2019-09-271-0/+2
* | | | | Merge pull request #1417 from YosysHQ/clifford/fixasync2syncClifford Wolf2019-09-301-0/+1
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| * | | | | Fix $dlatch handling in async2syncClifford Wolf2019-09-301-0/+1
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* | | | | Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
* | | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
* | | | | synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-303-2/+77
* | | | | Merge pull request #1414 from hzeller/improve-replace-with-empty-mapEddie Hung2019-09-291-0/+2
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