aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
| * | | | | Move Pass::call() out of abc9_ops into abc9Eddie Hung2019-12-303-68/+63
| * | | | | CleanupEddie Hung2019-12-301-7/+3
| * | | | | Use function argEddie Hung2019-12-301-9/+9
| * | | | | holes_module to be whiteboxEddie Hung2019-12-301-0/+10
| * | | | | Rid unnecessary ifEddie Hung2019-12-301-13/+11
| * | | | | Get rid of holes_modeEddie Hung2019-12-301-70/+35
| * | | | | Add abc9_ops -prep_holesEddie Hung2019-12-303-135/+321
| * | | | | Add abc9_ops -prep_dffEddie Hung2019-12-303-39/+50
| * | | | | Restore count_outputs, move process check to abcEddie Hung2019-12-302-11/+13
| * | | | | Fix struct nameEddie Hung2019-12-301-3/+3
| * | | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-3018-751/+1411
| |\| | | |
| | * | | | write_xaiger to use scratchpad for stats; cleanup abc9Eddie Hung2019-12-302-190/+20
| | * | | | Remove submod changesEddie Hung2019-12-302-201/+37
| | * | | | Remove unusedEddie Hung2019-12-301-5/+0
| | * | | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
| | * | | | Call "proc" if processes inside whiteboxesEddie Hung2019-12-301-1/+1
| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3042-211/+1731
| | |\ \ \ \
| | * | | | | Add CHANGELOG entry, add abc9_{flop,keep} attr to README.mdEddie Hung2019-12-302-0/+7
| | * | | | | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
| | * | | | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-304-53/+120
| | * | | | | GrammarEddie Hung2019-12-301-1/+1
| | * | | | | Really fix it!Eddie Hung2019-12-271-10/+7
| | * | | | | write_xaiger: fix arrival times for non boxesEddie Hung2019-12-271-18/+25
| | * | | | | Disable clock domain partitioning in Yosys pass, let ABC do itEddie Hung2019-12-231-6/+22
| | * | | | | write_xaiger to opt instead of just clean whiteboxesEddie Hung2019-12-231-1/+1
| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
| | |\ \ \ \ \
| | * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-2011-216/+339
| | |\ \ \ \ \ \
| | * | | | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
| | * | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-196-41/+60
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1947-161/+2030
| | |\ \ \ \ \ \ \
| | * | | | | | | | Bump ABC againEddie Hung2019-12-181-1/+1
| | * | | | | | | | Remove &verify -sEddie Hung2019-12-171-1/+1
| | * | | | | | | | Bump ABC for upstream fixEddie Hung2019-12-171-1/+1
| | * | | | | | | | Use pool<> instead of std::set<> to preserver orderingEddie Hung2019-12-171-6/+6
| | * | | | | | | | aiger frontend to user shorter, $-prefixed, namesEddie Hung2019-12-171-14/+14
| | * | | | | | | | Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-172-84/+24
| | * | | | | | | | read_xaiger to cope with optional '\n' after 'c'Eddie Hung2019-12-171-2/+2
| | * | | | | | | | Do not sigmapEddie Hung2019-12-171-1/+1
| | * | | | | | | | Revert "Use sigmap signal"Eddie Hung2019-12-171-1/+1
| | * | | | | | | | abc9 needs a clean afterwardsEddie Hung2019-12-161-2/+4
| | * | | | | | | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
| | * | | | | | | | Use sigmap signalEddie Hung2019-12-161-1/+1
| | * | | | | | | | Skip $inout transformation if not a PIEddie Hung2019-12-161-3/+5
| | * | | | | | | | Revert "write_xaiger: use sigmap bits more consistently"Eddie Hung2019-12-161-4/+5
| | * | | | | | | | write_xaiger: use sigmap bits more consistentlyEddie Hung2019-12-161-5/+4
| | * | | | | | | | Name inputs/outputs of aiger 'i%d' and 'o%d'Eddie Hung2019-12-131-13/+6
| | * | | | | | | | Remove 'clkpart' entry in CHANGELOGEddie Hung2019-12-121-1/+0
| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1218-64/+238
| | |\ \ \ \ \ \ \ \ | | | | |_|_|_|_|_|/ | | | |/| | | | | |
| | * | | | | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
| | * | | | | | | | Fix commentEddie Hung2019-12-091-1/+1