diff options
author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:13:16 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:13:16 -0800 |
commit | d7ada6649766cfa32b077a744e066476278afd02 (patch) | |
tree | 02c3b465d2cbcd2a29a58918c6a717bfd1251bfd | |
parent | 52a27700e2b985d56821ffefb3c61f88cfb96e1a (diff) | |
download | yosys-d7ada6649766cfa32b077a744e066476278afd02.tar.gz yosys-d7ada6649766cfa32b077a744e066476278afd02.tar.bz2 yosys-d7ada6649766cfa32b077a744e066476278afd02.zip |
Add "synth_xilinx -dff" option, cleanup abc9
-rw-r--r-- | backends/aiger/xaiger.cc | 5 | ||||
-rw-r--r-- | passes/techmap/abc9.cc | 68 | ||||
-rw-r--r-- | techlibs/xilinx/abc9_map.v | 84 | ||||
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 16 |
4 files changed, 120 insertions, 53 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 80077c10a..d27e0cde5 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -251,7 +251,7 @@ struct XAigerWriter RTLIL::Module* inst_module = module->design->module(cell->type); if (inst_module) { - bool abc9_box = inst_module->attributes.count("\\abc9_box_id"); + bool abc9_box = inst_module->attributes.count("\\abc9_box_id") && !cell->get_bool_attribute("\\abc9_keep"); for (const auto &conn : cell->connections()) { auto port_wire = inst_module->wire(conn.first); @@ -403,7 +403,8 @@ struct XAigerWriter log_assert(cell); RTLIL::Module* box_module = module->design->module(cell->type); - if (!box_module || !box_module->attributes.count("\\abc9_box_id")) + if (!box_module || !box_module->attributes.count("\\abc9_box_id") + || cell->get_bool_attribute("\\abc9_keep")) continue; bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 857f1a0a6..19a1d2ccb 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -249,9 +249,8 @@ struct abc9_output_filter }; void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file, - bool cleanup, vector<int> lut_costs, bool /*dff_mode*/, std::string /*clk_str*/, - bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, - bool show_tempdir, std::string box_file, std::string lut_file, + bool cleanup, vector<int> lut_costs, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, + const std::vector<RTLIL::Cell*> &/*cells*/, bool show_tempdir, std::string box_file, std::string lut_file, std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs ) { @@ -294,20 +293,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip } else abc9_script += stringf("source %s", script_file.c_str()); } else if (!lut_costs.empty() || !lut_file.empty()) { - //bool all_luts_cost_same = true; - //for (int this_cost : lut_costs) - // if (this_cost != lut_costs.front()) - // all_luts_cost_same = false; abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT; - //if (all_luts_cost_same && !fast_mode) - // abc9_script += "; lutpack {S}"; } else log_abort(); - //if (script_file.empty() && !delay_target.empty()) - // for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1)) - // abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8); - for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos)) abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3); @@ -439,8 +428,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip RTLIL::Module* box_module = design->module(cell->type); jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first; } - if (jt->second) - boxes.emplace_back(cell); + if (jt->second) { + auto kt = cell->attributes.find("\\abc9_keep"); + bool abc9_keep = false; + if (kt != cell->attributes.end()) { + abc9_keep = kt->second.as_bool(); + cell->attributes.erase(kt); + } + if (!abc9_keep) + boxes.emplace_back(cell); + } } dict<SigBit, pool<IdString>> bit_drivers, bit_users; @@ -766,7 +763,7 @@ struct Abc9Pass : public Pass { log(" if no -script parameter is given, the following scripts are used:\n"); log("\n"); log(" for -lut/-luts (only one LUT size):\n"); - log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str()); + log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str()); log("\n"); log(" for -lut/-luts (different LUT sizes):\n"); log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str()); @@ -782,8 +779,6 @@ struct Abc9Pass : public Pass { log(" set delay target. the string {D} in the default scripts above is\n"); log(" replaced by this option when used, and an empty string otherwise\n"); log(" (indicating best possible delay).\n"); -// log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n"); -// log(" default scripts above.\n"); log("\n"); // log(" -S <num>\n"); // log(" maximum number of LUT inputs shared.\n"); @@ -805,19 +800,6 @@ struct Abc9Pass : public Pass { log(" generate netlist using luts. Use the specified costs for luts with 1,\n"); log(" 2, 3, .. inputs.\n"); log("\n"); -// log(" -dff\n"); -// log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n"); -// log(" clock domains are automatically partitioned in clock domains and each\n"); -// log(" domain is passed through ABC independently.\n"); -// log("\n"); -// log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n"); -// log(" use only the specified clock domain. this is like -dff, but only FF\n"); -// log(" cells that belong to the specified clock domain are used.\n"); -// log("\n"); -// log(" -keepff\n"); -// log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n"); -// log(" them, for example for equivalence checking.)\n"); -// log("\n"); log(" -nocleanup\n"); log(" when this option is used, the temporary files created by this pass\n"); log(" are not removed. this is useful for debugging.\n"); @@ -865,7 +847,7 @@ struct Abc9Pass : public Pass { #endif std::string script_file, clk_str, box_file, lut_file; std::string delay_target, lutin_shared = "-S 1", wire_delay; - bool fast_mode = false, /*dff_mode = false,*/ keepff = false, cleanup = true; + bool fast_mode = false, cleanup = true; bool show_tempdir = false; bool nomfs = false; vector<int> lut_costs; @@ -956,19 +938,6 @@ struct Abc9Pass : public Pass { fast_mode = true; continue; } - //if (arg == "-dff") { - // dff_mode = true; - // continue; - //} - //if (arg == "-clk" && argidx+1 < args.size()) { - // clk_str = args[++argidx]; - // dff_mode = true; - // continue; - //} - //if (arg == "-keepff") { - // keepff = true; - // continue; - //} if (arg == "-nocleanup") { cleanup = false; continue; @@ -1083,7 +1052,7 @@ struct Abc9Pass : public Pass { typedef SigSpec clkdomain_t; dict<clkdomain_t, int> clk_to_mergeability; - std::vector<RTLIL::Cell*> all_cells = module->selected_cells(); + const std::vector<RTLIL::Cell*> all_cells = module->selected_cells(); #if 0 pool<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end()); @@ -1116,7 +1085,8 @@ struct Abc9Pass : public Pass { for (auto cell : all_cells) { auto inst_module = design->module(cell->type); - if (!inst_module || !inst_module->attributes.count("\\abc9_flop")) + if (!inst_module || !inst_module->attributes.count("\\abc9_flop") + || cell->get_bool_attribute("\\abc9_keep")) continue; Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str())); @@ -1268,8 +1238,8 @@ struct Abc9Pass : public Pass { RTLIL::Selection& sel = design->selection_stack.back(); sel.selected_members[module->name] = std::move(it.second); #endif - abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, false, "$", - keepff, delay_target, lutin_shared, fast_mode, show_tempdir, + abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, + delay_target, lutin_shared, fast_mode, all_cells, show_tempdir, box_file, lut_file, wire_delay, box_lookup, nomfs); #if 0 assign_map.set(module); diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index d2d7d9114..1e17d4766 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -83,6 +83,7 @@ module FDRE (output Q, input C, CE, D, R); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -113,9 +114,21 @@ module FDRE (output Q, input C, CE, D, R); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDRE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_R_INVERTED(IS_R_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .R(R) + ); +`endif endmodule module FDRE_1 (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -140,6 +153,14 @@ module FDRE_1 (output Q, input C, CE, D, R); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDRE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .R(R) + ); +`endif endmodule module FDCE (output Q, input C, CE, D, CLR); @@ -147,6 +168,7 @@ module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -190,9 +212,21 @@ module FDCE (output Q, input C, CE, D, CLR); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDCE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_CLR_INVERTED(IS_CLR_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) + ); +`endif endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -228,6 +262,14 @@ module FDCE_1 (output Q, input C, CE, D, CLR); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDCE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) + ); +`endif endmodule module FDPE (output Q, input C, CE, D, PRE); @@ -235,6 +277,7 @@ module FDPE (output Q, input C, CE, D, PRE); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -276,9 +319,21 @@ module FDPE (output Q, input C, CE, D, PRE); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDPE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_PRE_INVERTED(IS_PRE_INVERTED), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) + ); +`endif endmodule module FDPE_1 (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -314,6 +369,14 @@ module FDPE_1 (output Q, input C, CE, D, PRE); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDPE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) + ); +`endif endmodule module FDSE (output Q, input C, CE, D, S); @@ -321,6 +384,7 @@ module FDSE (output Q, input C, CE, D, S); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -350,9 +414,21 @@ module FDSE (output Q, input C, CE, D, S); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDSE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_S_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .S(S) + ); +`endif endmodule module FDSE_1 (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -376,6 +452,14 @@ module FDSE_1 (output Q, input C, CE, D, S); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDSE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .S(S) + ); +`endif endmodule module RAM32X1D ( diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ac6fedc58..e7069f286 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -109,6 +109,9 @@ struct SynthXilinxPass : public ScriptPass log(" -flatten\n"); log(" flatten design before synthesis\n"); log("\n"); + log(" -dff\n"); + log(" run 'abc9' with -dff option\n"); + log("\n"); log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); @@ -122,7 +125,8 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9; + bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram; + bool abc9, dff_mode; bool flatten_before_abc; int widemux; @@ -148,6 +152,7 @@ struct SynthXilinxPass : public ScriptPass nodsp = false; uram = false; abc9 = false; + dff_mode = false; flatten_before_abc = false; widemux = 0; } @@ -256,6 +261,10 @@ struct SynthXilinxPass : public ScriptPass uram = true; continue; } + if (args[argidx] == "-dff") { + dff_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -540,7 +549,10 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); - run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); + std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1"; + if (dff_mode) + techmap_args += " -D DFF_MODE"; + run("techmap " + techmap_args); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); |