aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* write_xaiger to opt instead of just clean whiteboxesEddie Hung2019-12-231-1/+1
|
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
|\
| * Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
| |
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-2011-216/+339
|\|
| * Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
| |
| * Put specify/endspecify inside ``Eddie Hung2019-12-201-4/+4
| |
| * Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lutEddie Hung2019-12-201-19/+18
| |\ | | | | | | Interpret "abc9 -lut" as lut string only if [0-9:]
| | * Interpret "abc9 -lut" as lut string only if [0-9:]Eddie Hung2019-12-181-19/+18
| | |
| * | Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanupEddie Hung2019-12-204-39/+21
| |\ \ | | | | | | | | Revert "Optimise write_xaiger"
| | * | Revert "Optimise write_xaiger"Eddie Hung2019-12-204-39/+21
| |/ /
| * | Fix linking with Python 3.8Graham Edgecombe2019-12-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The behaviour of python-config --libs has changed in Python 3.8. For example, compare the output of it with Python 3.7 and 3.8 on an ArchLinux system: $ python3.7-config --libs -lpython3.7m -lcrypt -lpthread -ldl -lutil -lm $ python3.8-config --libs -lcrypt -lpthread -ldl -lutil -lm -lm $ The lack of -lpython in the latter case causes the linker to fail when attempting to build Yosys against Python 3.8. Passing the new --embed flag to python-config adds -lpython, just like earlier versions of Python: $ python3.8-config --embed --libs -lpython3.8 -lcrypt -lpthread -ldl -lutil -lm -lm $ This commit adds code for automatically detecting support for the --embed flag. If it is supported, it is passed to all python-config invocations. This fixes building against Python 3.8.
| * | Add PYTHON_CONFIG variable to the MakefileGraham Edgecombe2019-12-201-17/+18
| | |
| * | Merge pull request #1581 from YosysHQ/clifford/fix1565Eddie Hung2019-12-191-1/+1
| |\ \ | | | | | | | | Fix sim for assignments with lhs<rhs size
| | * | Fix sim for assignments with lhs<rhs size, fixes #1565Clifford Wolf2019-12-171-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-194-21/+39
| |\ \ \ | | | | | | | | | | Optimise write_xaiger
| | * | | Stray newlineEddie Hung2019-12-061-1/+0
| | | | |
| | * | | write_xaiger to inst each cell type once, do not call techmap/aigmapEddie Hung2019-12-061-21/+25
| | | | |
| | * | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
| | | | |
| * | | | Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-192-0/+50
| |\ \ \ \ | | | | | | | | | | | | verilog: preserve size of $genval$-s in for loops
| | * | | | Stray log_dumpEddie Hung2019-12-111-1/+0
| | | | | |
| | * | | | Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
| | | | | |
| | * | | | Add testcaseEddie Hung2019-12-111-0/+34
| | | | | |
| * | | | | Merge pull request #1571 from YosysHQ/eddie/fix_1570Eddie Hung2019-12-191-3/+1
| |\ \ \ \ \ | | | | | | | | | | | | | | mem_arst.v: do not redeclare ANSI port
| | * | | | | Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
| | | | | | |
| * | | | | | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
| | | | | | |
| * | | | | | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
* | | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
| | | | | |
* | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-196-41/+60
| | | | | |
* | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1947-161/+2030
|\| | | | |
| * | | | | Add "scratchpad" to CHANGELOGEddie Hung2019-12-181-0/+1
| | | | | |
| * | | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-1824-84/+1071
| |\ \ \ \ \
| | * \ \ \ \ Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs
| | | * | | | | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | Merge pull request #1572 from nakengelhardt/scratchpad_passEddie Hung2019-12-183-0/+136
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | add a command to read/modify scratchpad contents
| | | * | | | | | use extra_argsN. Engelhardt2019-12-181-1/+1
| | | | | | | | |
| | | * | | | | | add assert option to scratchpad commandN. Engelhardt2019-12-163-19/+49
| | | | | | | | |
| | | * | | | | | add periods and newlines to help messageN. Engelhardt2019-12-131-5/+5
| | | | | | | | |
| | | * | | | | | add test and make help message more verboseN. Engelhardt2019-12-122-1/+20
| | | | | | | | |
| | | * | | | | | add a command to read/modify scratchpad contentsN. Engelhardt2019-12-122-0/+87
| | | | |/ / / / | | | |/| | | |
| | * | | | | | Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-testEddie Hung2019-12-181-2/+4
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | tests/xilinx: fix flaky mux test
| | | * | | | | | tests/xilinx: fix flaky mux testMarcin Kościelnicki2019-12-181-2/+4
| | |/ / / / / /
| | * | | | | | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-1811-27/+638
| | | | | | | |
| | * | | | | | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-188-49/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
| | * | | | | | Send people to symbioticeda.com instead of verific.comClifford Wolf2019-12-182-5/+26
| | | |_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / | | | | CleanupEddie Hung2019-12-171-11/+7
| |/ / / / /
| * | | | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-1613-65/+529
| |\ \ \ \ \ | | | | | | | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| | * \ \ \ \ Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵Eddie Hung2019-12-161-2/+8
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | eddie/xilinx_lutram
| | | * | | | | Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
| | | | | | | |
| | * | | | | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
| | |/ / / / /
| | * | | | | Disable RAM16X1D testEddie Hung2019-12-131-17/+17
| | | | | | |
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 06:44:02 +0000