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authorMarcin Koƛcielnicki <mwk@0x04.net>2019-12-18 15:53:20 +0100
committerMarcin Koƛcielnicki <mwk@0x04.net>2019-12-18 15:53:29 +0100
commitf382164d6ed4e6fd6820322db5becf081a74f272 (patch)
tree201cef00297b4e9e4f649783a0887756a7e0b088
parenta2352504031ee69efd0aac214fc947737303eb5e (diff)
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tests/xilinx: fix flaky mux test
-rw-r--r--tests/arch/xilinx/mux.ys6
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index 821d0fab7..388272449 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -40,6 +40,8 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 5 t:LUT6
+select -assert-min 5 t:LUT6
+select -assert-max 7 t:LUT6
+select -assert-max 2 t:MUXF7
-select -assert-none t:LUT6 %% t:* %D
+select -assert-none t:LUT6 t:MUXF7 %% t:* %D