| Commit message (Collapse) | Author | Age | Files | Lines |
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Updates from official repo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Changes for MXE configuration in order to compile
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Add support for 64-bit builds using msys2 environment, use msys-provided `libpthread`.
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Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
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Fix remaining log_file_error(); emit dependent file references in new…
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There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
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Gate POSIX-only signals and resource module to only run on POSIX Pyth…
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implementations.
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fix basys3 example
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Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file
to avoid warning `DRC 23-20`.
Added `open_hw` needed for programming.
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
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No longer false warnings for memories and assertions
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to be moved out of the tests/simple dir that only runs Verilog files
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It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
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Detect illegal port declaration, e.g input/output/inout keyword must …
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first.
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Map .eblif extension as blif.
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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#565 Add BLIF parsing support for .conn and .cname
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
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Use `realpath`
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Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager.
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readme: Fix formatting of a keyword
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Single quotes were used instead of backticks leading to
incorrect formatting.
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Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Convert more log_error() to log_file_error() where possible.
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Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
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Use log_file_warning(), log_file_error() functions
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Wherever we can report a source-level location.
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Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Merging with official repo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Adding ECP5 synthesis target
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Signed-off-by: David Shah <davey1576@gmail.com>
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