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| author | David Shah <davey1576@gmail.com> | 2018-07-16 15:56:12 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-07-16 15:56:12 +0200 |
| commit | 3a3558acce25807d6ce75280cc3f43aeb52974df (patch) | |
| tree | 157f95dcd722e60b8dd184196d6369d3f022b6a0 | |
| parent | e9ef077266652b4a76773287199a0b7f18b94a3d (diff) | |
| download | yosys-3a3558acce25807d6ce75280cc3f43aeb52974df.tar.gz yosys-3a3558acce25807d6ce75280cc3f43aeb52974df.tar.bz2 yosys-3a3558acce25807d6ce75280cc3f43aeb52974df.zip | |
ecp5: Fixing miscellaneous sim model issues
Signed-off-by: David Shah <davey1576@gmail.com>
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index cf1446a52..1700694e8 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); always @(posedge muxclk, posedge muxlsr) if (muxlsr) Q <= srval; - else + else if (muxce) Q <= DI; end else begin always @(posedge muxclk) if (muxlsr) Q <= srval; - else + else if (muxce) Q <= DI; end endgenerate |