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| author | Udi Finkelstein <github@udifink.com> | 2018-06-06 22:27:25 +0300 |
|---|---|---|
| committer | Udi Finkelstein <github@udifink.com> | 2018-06-06 22:27:25 +0300 |
| commit | 8b7580b0a152ec937abb1510abf5f2d7cd3b7acb (patch) | |
| tree | f9a62e951c77a20749fdbf3d1df76786b7a298c7 | |
| parent | 270c1814b5bcab0f0b54f05b4856380b57617a69 (diff) | |
| download | yosys-8b7580b0a152ec937abb1510abf5f2d7cd3b7acb.tar.gz yosys-8b7580b0a152ec937abb1510abf5f2d7cd3b7acb.tar.bz2 yosys-8b7580b0a152ec937abb1510abf5f2d7cd3b7acb.zip | |
Detect illegal port declaration, e.g input/output/inout keyword must be the first.
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e803d8072..72a501d11 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -376,9 +376,10 @@ wire_type: }; wire_type_token_list: - wire_type_token | wire_type_token_list wire_type_token; + wire_type_token | wire_type_token_list wire_type_token | + wire_type_token_io ; -wire_type_token: +wire_type_token_io: TOK_INPUT { astbuf3->is_input = true; } | @@ -388,7 +389,9 @@ wire_type_token: TOK_INOUT { astbuf3->is_input = true; astbuf3->is_output = true; - } | + }; + +wire_type_token: TOK_WIRE { } | TOK_REG { |