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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-06 10:41:53 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-06 10:41:53 +0200 |
| commit | 63f4cc38eb3afe66642fea8d130fda623c6f825a (patch) | |
| tree | c8f9adf27b2a218c73818f3b6fc0dd4d4824892b | |
| parent | e275692e84c935d0cdf42c2a4adf7ac949a88132 (diff) | |
| parent | da53206cd4b1e32d8bf29bb33cdfec81d614525e (diff) | |
| download | yosys-63f4cc38eb3afe66642fea8d130fda623c6f825a.tar.gz yosys-63f4cc38eb3afe66642fea8d130fda623c6f825a.tar.bz2 yosys-63f4cc38eb3afe66642fea8d130fda623c6f825a.zip | |
Merge pull request #599 from kbeckmann/kbeckmann/fix_readme_quotes
readme: Fix formatting of a keyword
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -389,7 +389,7 @@ Verilog Attributes and non-standard features Non-standard or SystemVerilog features for formal verification ============================================================== -- Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled +- Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled when ``read_verilog`` is called with ``-formal``. - The system task ``$initstate`` evaluates to 1 in the initial state and |