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| * | Fix Verific handling of single-bit anyseq/anyconst wiresClifford Wolf2018-05-251-2/+4
| * | Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGEClifford Wolf2018-05-241-1/+1
| * | Fix verific handling of anyconst/anyseq attributesClifford Wolf2018-05-242-16/+28
| * | Merge pull request #454 from rqou/emscripten-and-abcClifford Wolf2018-05-194-15/+87
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| | * | Force abc to align memory to 8 bytesRobert Ou2018-05-181-1/+1
| | * | Modify emscripten main to mount nodefs and to run arg as a scriptRobert Ou2018-05-181-1/+18
| | * | Force abc to be linked statically and without threads in emscriptenRobert Ou2018-05-181-0/+5
| | * | Fix infinite loop in abc command under emscriptenRobert Ou2018-05-181-5/+7
| | * | Fix reading techlibs under emscriptenRobert Ou2018-05-181-1/+1
| | * | Add options to disable abc's usage of pthreads and readlineRobert Ou2018-05-181-0/+10
| | * | Add an option to statically link abc into yosysRobert Ou2018-05-182-4/+38
| | * | Makefile: Make abc always use stdint.hRobert Ou2018-05-181-4/+8
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| * | Merge pull request #550 from jimparis/yosys-upstreamClifford Wolf2018-05-171-1/+6
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| | * | Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
| | * | Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
| * | | Merge pull request #551 from olofk/ice40_cells_sim_portsClifford Wolf2018-05-171-43/+23
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| | * | Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
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| * | Fix handling of anyconst/anyseq attrs in VHDL code via VerificClifford Wolf2018-05-151-6/+6
| * | Remove mercurial from build instructionsClifford Wolf2018-05-151-3/+3
| * | Fix iopadmap for loops between tristate IO buffersClifford Wolf2018-05-151-0/+21
| * | Fix iopadmap for cases where IO pins already have buffers on themClifford Wolf2018-05-151-1/+35
* | | Correction to -expose with setundefAman Goel2018-05-151-0/+1
* | | Minor correctionAman Goel2018-05-141-2/+1
* | | Corrections to option -expose in setundef passAman Goel2018-05-131-16/+141
* | | Add option -expose to setundef passAman Goel2018-05-131-6/+26
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* | Some cleanups in setundef.ccClifford Wolf2018-05-131-0/+7
* | Use $(OS) in makefile to check for DarwinClifford Wolf2018-05-131-1/+1
* | Merge pull request #505 from thefallenidealist/FreeBSD_buildClifford Wolf2018-05-133-2/+26
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| * | update READMEJohnny Sorocil2018-05-061-0/+8
| * | autotest.sh: Change from /bin/bash to /usr/bin/env bashJohnny Sorocil2018-05-061-1/+1
| * | Enable building on FreeBSDJohnny Sorocil2018-05-061-1/+17
* | | Add "#ifdef __FreeBSD__"Christian Krämer2018-05-135-9/+52
* | | Revert "Add "#ifdef __FreeBSD__""Clifford Wolf2018-05-135-52/+9
* | | Also interpret '&' in liberty functionsSergiusz Bazanski2018-05-121-1/+1
* | | Add optimization of tristate buffer with constant control inputClifford Wolf2018-05-121-0/+17
* | | Add "hierarchy -simcheck"Clifford Wolf2018-05-121-7/+23
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* | Further improve handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-69/+108
* | Fix handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-26/+46
* | Add "#ifdef __FreeBSD__"Johnny Sorocil2018-05-055-9/+52
* | Add ABC FAQ to "help abc"Clifford Wolf2018-05-041-2/+6
* | Add "yosys -e regex" for turning warnings into errorsClifford Wolf2018-05-043-4/+22
* | Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
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| * | Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| * | synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
* | | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-035-21/+58
* | | Support more character literalsDan Gisselquist2018-05-031-1/+9
* | | Update ABC to git rev f23ea8eClifford Wolf2018-04-301-1/+1
* | | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
* | | Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
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* | Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
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