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| author | Jim Paris <jim@jtan.com> | 2018-05-17 00:06:49 -0400 |
|---|---|---|
| committer | Jim Paris <jim@jtan.com> | 2018-05-17 00:06:49 -0400 |
| commit | 872d8d49e98fc5a4090ce20d902afbd0090c8c84 (patch) | |
| tree | 222e015a798f8498fc5376c9e2e668ec645b930d | |
| parent | a7281930c5877b34e072d90d5ca013f8fda7e2cc (diff) | |
| download | yosys-872d8d49e98fc5a4090ce20d902afbd0090c8c84.tar.gz yosys-872d8d49e98fc5a4090ce20d902afbd0090c8c84.tar.bz2 yosys-872d8d49e98fc5a4090ce20d902afbd0090c8c84.zip | |
Skip spaces around macro arguments
| -rw-r--r-- | frontends/verilog/preproc.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index c43ff4e3a..00124cb42 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -244,6 +244,7 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args, args.push_back(std::string()); while (1) { + skip_spaces(); tok = next_token(true); if (tok == ")" || tok == "}" || tok == "]") level--; |