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authorJim Paris <jim@jtan.com>2018-05-17 00:09:56 -0400
committerJim Paris <jim@jtan.com>2018-05-17 00:09:56 -0400
commit4a229e5b953c15ecb31945258e0ca2f7bffe8a3e (patch)
tree367112f4f46fc2af890ebad1fb86e496d36ce3ad
parent872d8d49e98fc5a4090ce20d902afbd0090c8c84 (diff)
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Support SystemVerilog `` extension for macros
-rw-r--r--frontends/verilog/preproc.cc6
1 files changed, 5 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 00124cb42..dea22ee8a 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -183,8 +183,9 @@ static std::string next_token(bool pass_newline = false)
const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789";
if (ch == '`' || strchr(ok, ch) != NULL)
{
+ char first = ch;
ch = next_char();
- if (ch == '"') {
+ if (first == '`' && (ch == '"' || ch == '`')) {
token += ch;
} else do {
if (strchr(ok, ch) == NULL) {
@@ -265,6 +266,9 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
}
insert_input(defines_map[name]);
return true;
+ } else if (tok == "``") {
+ // Swallow `` in macro expansion
+ return true;
} else return false;
}