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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-2514-10/+80
* Add "write_smt2 -stbv"Clifford Wolf2017-02-243-49/+179
* Add SMT2 statebv mode (inactive for now)Clifford Wolf2017-02-241-20/+47
* Merge pull request #320 from joshhead/uninstall-binpath-fixClifford Wolf2017-02-241-1/+1
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| * Add missing slashes in paths for make uninstallJosh Headapohl2017-02-231-1/+1
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* Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-232-4/+25
* Preserve string parametersClifford Wolf2017-02-231-2/+8
* Fix mingw compile issue (2nd attempt)Clifford Wolf2017-02-231-2/+2
* Fix mingw compile issue (maybe.. I can't test it)Clifford Wolf2017-02-231-2/+2
* Added SystemVerilog support for ++ and --Clifford Wolf2017-02-232-1/+12
* Update ABC to hg rev 8da4dc435b9fClifford Wolf2017-02-221-1/+1
* Add "yosys-smtbmc -S <opt>"Clifford Wolf2017-02-191-7/+18
* Copy attributes to _TECHMAP_REPLACE_ cellsClifford Wolf2017-02-161-2/+8
* Fix eval implementation of $_NOR_Clifford Wolf2017-02-161-1/+1
* Fix incorrect "incompatible re-declaration of wire" error in tasks/functionsClifford Wolf2017-02-141-2/+9
* Add warning about x/z bits left unconnected in EDIF outputClifford Wolf2017-02-141-2/+5
* Fix double-call of log_pop() in synth_greenpak4Clifford Wolf2017-02-141-2/+0
* Merge pull request #313 from azidar/bugfix-assign-wmaskClifford Wolf2017-02-143-27/+181
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| * More progress on Firrtl backend.Adam Izraelevitz2017-02-133-27/+181
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* Do not fix port widths on any blackbox instancesClifford Wolf2017-02-131-1/+1
* Fix techmap for inout ports connected to inout portsClifford Wolf2017-02-131-2/+7
* Do not eagerly fix port widths on parameterized cellsClifford Wolf2017-02-121-0/+3
* Add "yosys -w" for suppressing warningsClifford Wolf2017-02-123-11/+34
* Add support for verific mem initializationClifford Wolf2017-02-111-0/+38
* Fix another stupid bug in the same lineClifford Wolf2017-02-111-1/+1
* Add verific support for initialized variablesClifford Wolf2017-02-111-3/+47
* Improve handling of Verific warnings and error messagesClifford Wolf2017-02-111-4/+10
* Fix extremely stupid typoClifford Wolf2017-02-111-1/+1
* Add log_wire() APIClifford Wolf2017-02-112-0/+8
* Fixed some "used uninitialized" warnings in opt_exprClifford Wolf2017-02-111-1/+2
* Evaluate all the $(shell ...) stuff for CXXFLAGS et al only onceClifford Wolf2017-02-111-3/+3
* Merge branch 'stv0g-master'Clifford Wolf2017-02-112-21/+40
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| * Make MacOS Makefile stuff more compactClifford Wolf2017-02-111-8/+0
| * Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-masterClifford Wolf2017-02-112-21/+48
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| * Use pkg-config for linking tcl-tkSteffen Vogel2017-02-101-3/+5
| * Dont mix Homebrew and MacPorts build optionsSteffen Vogel2017-02-101-2/+1
| * Remove space after backslashSteffen Vogel2017-02-091-1/+1
| * Applied fixes from @joshhead (thanks for your effors!)Steffen Vogel2017-02-092-5/+7
| * Added notes for compilation on OS XSteffen Vogel2017-02-071-3/+13
| * Fix compilation on OS X in order to support both MacPorts and HomebrewSteffen Vogel2017-02-071-13/+25
| * Allow standard tools to be overwritten in make invocationSteffen Vogel2017-02-071-3/+3
| * use Homebrew only if installedSteffen Vogel2017-01-311-6/+8
* | Add optimization of (a && 1'b1) and (a || 1'b0)Clifford Wolf2017-02-111-7/+22
* | Merge pull request #308 from C-Elegans/opt_compare_fix_prClifford Wolf2017-02-111-1/+19
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| * | Fix issue #306, "Bug in opt -full"C-Elegans2017-02-101-1/+19
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* | Fix handling of init attributes with strange widthClifford Wolf2017-02-092-3/+9
* | Add checker support to verilog front-endClifford Wolf2017-02-093-14/+33
* | Add "rand" and "rand const" verific supportClifford Wolf2017-02-091-0/+41
* | Add SV "rand" and "const rand" supportClifford Wolf2017-02-083-10/+33
* | Add PSL parser mode to verific front-endClifford Wolf2017-02-081-2/+17
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