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authorClifford Wolf <clifford@clifford.at>2017-02-11 11:09:07 +0100
committerClifford Wolf <clifford@clifford.at>2017-02-11 11:09:07 +0100
commiteb7b18e897ac908e960bee6c976f744043590881 (patch)
tree0b389c8e7adf21191f573b97ef596aa21f446fe6
parent63dfdb5d7fcfb9c0ec2a5352a34cf9119e28766a (diff)
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Fix extremely stupid typo
-rw-r--r--frontends/verific/verific.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 3f5cf3f5f..306bc5d82 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -774,7 +774,7 @@ struct VerificImporter
SigBit outsig = net_map.at(out);
log_assert(outsig.wire && GetSize(outsig.wire) == 1);
- outsig.wire->attributes["\\init"] == Const(0, 1);
+ outsig.wire->attributes["\\init"] = Const(0, 1);
module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
continue;