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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-11 10:50:48 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-11 10:50:48 +0100 |
| commit | 95dae6d416bd9e9ca08fea9ab354b6de7e433fdb (patch) | |
| tree | e485fc3483509dda8603c8b0fc4bc0de56b9e8e0 | |
| parent | 6d4e8673cc1c73df7509b016bd7cc9e67f6384d7 (diff) | |
| download | yosys-95dae6d416bd9e9ca08fea9ab354b6de7e433fdb.tar.gz yosys-95dae6d416bd9e9ca08fea9ab354b6de7e433fdb.tar.bz2 yosys-95dae6d416bd9e9ca08fea9ab354b6de7e433fdb.zip | |
Fixed some "used uninitialized" warnings in opt_expr
| -rw-r--r-- | passes/opt/opt_expr.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 9ccc230e8..236908060 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1242,7 +1242,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons width = cell->parameters["\\B_WIDTH"].as_int(); const_width = cell->parameters["\\A_WIDTH"].as_int(); var_signed = cell->parameters["\\B_SIGNED"].as_bool(); - } + } else + log_abort(); // replace a(signed) < 0 with the high bit of a if (sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true) |