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author | Clifford Wolf <clifford@clifford.at> | 2017-02-13 17:07:38 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-02-13 17:07:38 +0100 |
commit | 69468d5a16f87616af9c7f084f6ff247f3513050 (patch) | |
tree | 7e972247a3c0b6f04cf4cdc4cee532b870cf0430 | |
parent | db7314bc02b4e8b1827993cd844eac9c7070579f (diff) | |
download | yosys-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz yosys-69468d5a16f87616af9c7f084f6ff247f3513050.tar.bz2 yosys-69468d5a16f87616af9c7f084f6ff247f3513050.zip |
Do not fix port widths on any blackbox instances
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 037fdb3b2..3534cbcdb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -630,7 +630,7 @@ struct HierarchyPass : public Pass { Module *m = design->module(cell->type); - if (m == nullptr) + if (m == nullptr || m->get_bool_attribute("\\blackbox")) continue; for (auto &conn : cell->connections()) |