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* Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
* Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dspEddie Hung2019-07-193-5/+29
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| * Add another testEddie Hung2019-07-191-1/+24
| * Do not access beyond boundsEddie Hung2019-07-191-1/+1
| * Add an SigSpec::at(offset, defval) convenience methodEddie Hung2019-07-191-0/+1
| * Wrap A and B in sigmapEddie Hung2019-07-191-2/+2
| * Remove "top" from messageEddie Hung2019-07-191-1/+1
* | Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dspEddie Hung2019-07-192-3/+121
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| * Also optimise MSB of $subEddie Hung2019-07-191-3/+3
| * Add one more test with trimming Y_WIDTH of $subEddie Hung2019-07-191-11/+14
| * Be more explicitEddie Hung2019-07-191-6/+29
| * wreduce for $subEddie Hung2019-07-191-0/+23
| * Add tests for sub tooEddie Hung2019-07-191-1/+48
| * Add testEddie Hung2019-07-191-0/+22
| * SigSpec::extract to take negative lengthsEddie Hung2019-07-191-1/+1
* | Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
* | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
* | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
* | Fine tune ice40_dsp.pmg, add support for packing subsets of registersEddie Hung2019-07-194-35/+47
* | Add support for ice40 signed multipliersEddie Hung2019-07-191-13/+8
* | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| * | Fix typo in BEddie Hung2019-07-191-1/+1
| * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1829-228/+405
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* | | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| * | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| * | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| * | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
| * | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
* | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
* | | Add paramsEddie Hung2019-07-181-0/+6
* | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| | * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| | * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| | * | synth_intel: revert change to run_max10Dan Ravensloft2019-07-181-1/+1
| | * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-182-29/+11
| | * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| * | | Merge pull request #1207 from ZirconiumX/intel_new_pass_namesDavid Shah2019-07-181-4/+4
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| | * | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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* | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
* | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1828-195/+387
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| * | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
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| | * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
| | * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
| * | | Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
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| | * | | write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
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