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| author | Ben Widawsky <ben@bwidawsk.net> | 2019-07-08 12:03:00 -0700 |
|---|---|---|
| committer | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-07-18 17:05:54 +0100 |
| commit | 060e77c09b51aabe712315d5fd655f62a765d62f (patch) | |
| tree | 08282ed9dbfd584e7056e274eb0bd6f29a13c703 | |
| parent | e66e8fb59d8443c8d55c1185d6b2ce889a35357d (diff) | |
| download | yosys-060e77c09b51aabe712315d5fd655f62a765d62f.tar.gz yosys-060e77c09b51aabe712315d5fd655f62a765d62f.tar.bz2 yosys-060e77c09b51aabe712315d5fd655f62a765d62f.zip | |
intel_synth: Minor code cleanups
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 09c9ba3af..69f3b6334 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -147,8 +147,12 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" && - family_opt != "cycloneive" && family_opt != "cyclone10") + if (family_opt != "max10" && + family_opt != "a10gx" && + family_opt != "cyclonev" && + family_opt != "cycloneiv" && + family_opt != "cycloneive" && + family_opt != "cyclone10") log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); log_header(design, "Executing SYNTH_INTEL pass.\n"); |