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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 12:34:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 12:34:04 -0700 |
| commit | 25ff27e37fcb12c6a298267eda2464431304d713 (patch) | |
| tree | 1a42d05f93b08666dbd1139a82e708b12c1eaa62 | |
| parent | 9cb0456b6f9fa86240a747bab9780a28001b1a02 (diff) | |
| download | yosys-25ff27e37fcb12c6a298267eda2464431304d713.tar.gz yosys-25ff27e37fcb12c6a298267eda2464431304d713.tar.bz2 yosys-25ff27e37fcb12c6a298267eda2464431304d713.zip | |
SigSpec::extract to take negative lengths
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a09f4a0d1..85b013bdc 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,7 +3353,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length); + return std::vector<RTLIL::SigBit>(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) |