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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 11:54:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 11:54:26 -0700 |
| commit | bba72f03ddd6db370e8fd5afbf14f4f89d0c7e3e (patch) | |
| tree | 7072c63e6d463a414b0663451681a6e74379e3be | |
| parent | 3dc3c749d5c7c10e1aa504f48794ef0a87513a82 (diff) | |
| download | yosys-bba72f03ddd6db370e8fd5afbf14f4f89d0c7e3e.tar.gz yosys-bba72f03ddd6db370e8fd5afbf14f4f89d0c7e3e.tar.bz2 yosys-bba72f03ddd6db370e8fd5afbf14f4f89d0c7e3e.zip | |
Do not $mul -> $__mul if A and B are less than maxwidth
| -rw-r--r-- | techlibs/common/mul2dsp.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index aab568c9f..5444d842a 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -28,7 +28,9 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y;
generate
- if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
+ if (A_SIGNED != B_SIGNED)
+ wire _TECHMAP_FAIL_ = 1;
+ else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH)
wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED == 0 from here
else if (A_WIDTH >= B_WIDTH)
|