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* xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 onlyEddie Hung2020-04-221-1/+1
* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
* kernel: Cell::getParam() to throw exception again if not foundEddie Hung2020-04-221-3/+2
* Merge pull request #1949 from YosysHQ/eddie/select_blackboxEddie Hung2020-04-222-9/+54
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| * Update passes/cmds/select.ccClaire Wolf2020-04-221-2/+2
| * tests: update select black/white-box testsEddie Hung2020-04-221-0/+7
| * select: do not select black/white boxes by default, '=' prefix to do soEddie Hung2020-04-221-5/+5
| * Add '=' selection pattern prefix for non-blackbox only patternsClaire Wolf2020-04-211-12/+26
| * select: add test for not selecting inside black/white boxesEddie Hung2020-04-161-0/+21
| * select: do not select inside blackboxesEddie Hung2020-04-161-0/+3
* | Merge pull request #1983 from YosysHQ/eddie/use_default_paramEddie Hung2020-04-229-60/+54
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| * | Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-229-60/+54
* | | Merge pull request #1982 from AsuMagic/asu/cxxrtl-memory-queue-optwhitequark2020-04-221-3/+5
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| * | | cxxrtl: keep the memory write queue sorted on insertion.Asu2020-04-221-3/+5
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* | | Merge pull request #1969 from boqwxp/pool_emplaceEddie Hung2020-04-221-2/+32
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| * | pool: add emplace() functionEddie Hung2020-04-221-0/+6
| * | kernel: Rename arguments to rvalue-reference-accepting functions.Alberto Gonzalez2020-04-211-8/+8
| * | Add rvalue-reference-accepting `entry_t` constructor for `pool`.Alberto Gonzalez2020-04-201-0/+1
| * | In `pool`, construct `entry_t`s in-place and add an rvalue-accepting-and-forw...Alberto Gonzalez2020-04-201-2/+25
* | | Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-222-2/+4
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| * | | yosys-config: spellingEddie Hung2020-04-221-1/+1
| * | | tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
* | | | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-223-7/+30
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| * | | | design: add testEddie Hung2020-04-162-5/+22
| * | | | design: -import to not count black/white-boxes as candidates for topEddie Hung2020-04-161-2/+8
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* | | | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-222-1/+18
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| * | | | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-212-1/+18
* | | | | Merge pull request #1979 from whitequark/cxxrtl-go-fasterClaire Wolf2020-04-222-184/+396
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| * | | | | cxxrtl: run edge detectors only once in eval().whitequark2020-04-221-6/+22
| * | | | | cxxrtl: add an unsupported knob for manipulating clock trees.whitequark2020-04-221-0/+18
| * | | | | cxxrtl: use log_id() where appropriate. NFC.whitequark2020-04-211-4/+4
| * | | | | cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.whitequark2020-04-211-65/+186
| * | | | | cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.whitequark2020-04-211-23/+23
| * | | | | cxxrtl: use one delta cycle for immediately converging netlists.whitequark2020-04-212-11/+21
| * | | | | cxxrtl: add -O6, a shortcut for running `proc; flatten`.whitequark2020-04-211-4/+14
| * | | | | cxxrtl: unbuffer module input wires.whitequark2020-04-211-31/+61
| * | | | | cxxrtl: simplify generated edge detection logic.whitequark2020-04-211-56/+29
| * | | | | cxxrtl: localize wires with multiple comb drivers, too.whitequark2020-04-211-32/+31
| * | | | | cxxrtl: detect buffered comb wires, not just feedback wires.whitequark2020-04-211-5/+40
* | | | | | bugpoint: Don't remove modules or cells while iterating over them.Marcelina Kościelnicka2020-04-221-4/+14
* | | | | | intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
* | | | | | write_json: dump default parameter valuesMarcelina Kościelnicka2020-04-211-0/+10
* | | | | | Use default parameter value in getParamMarcelina Kościelnicka2020-04-212-4/+13
* | | | | | hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-212-3/+50
* | | | | | ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-216-9/+27
* | | | | | idict: Make iterator go forward.Marcelina Kościelnicka2020-04-211-5/+19
* | | | | | Merge pull request #1971 from YosysHQ/claire/edifkeepClaire Wolf2020-04-211-14/+108
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| * | | | | | Improve net priorities in EDIF back-endClaire Wolf2020-04-211-0/+64
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