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author | Claire Wolf <clifford@clifford.at> | 2020-04-21 19:04:55 +0200 |
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committer | GitHub <noreply@github.com> | 2020-04-21 19:04:55 +0200 |
commit | a6f9e28680c2700f903ffdaa837525b71708aa16 (patch) | |
tree | 4e9ab4271ab8044d0f5e2cc1a7a6ddbd0dc88022 | |
parent | 9e1afde7a02e6d3a65c106f74920dcad9e678a04 (diff) | |
parent | 27506d2aeb0eadac8dd110f1723b93feb583ef46 (diff) | |
download | yosys-a6f9e28680c2700f903ffdaa837525b71708aa16.tar.gz yosys-a6f9e28680c2700f903ffdaa837525b71708aa16.tar.bz2 yosys-a6f9e28680c2700f903ffdaa837525b71708aa16.zip |
Merge pull request #1971 from YosysHQ/claire/edifkeep
Ignore conflicting keep attributes, unless asked not to
-rw-r--r-- | backends/edif/edif.cc | 122 |
1 files changed, 108 insertions, 14 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index cc20f17fc..7e24468c0 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -113,6 +113,9 @@ struct EdifBackend : public Backend { log(" -attrprop\n"); log(" create EDIF properties for cell attributes\n"); log("\n"); + log(" -keep\n"); + log(" create extra KEEP nets by allowing a cell to drive multiple nets.\n"); + log("\n"); log(" -pvector {par|bra|ang}\n"); log(" sets the delimiting character for module port rename clauses to\n"); log(" parentheses, square brackets, or angle brackets.\n"); @@ -130,7 +133,7 @@ struct EdifBackend : public Backend { bool port_rename = false; bool attr_properties = false; std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports; - bool nogndvcc = false, gndvccy = false; + bool nogndvcc = false, gndvccy = false, keepmode = false; CellTypes ct(design); EdifNames edif_names; @@ -153,6 +156,10 @@ struct EdifBackend : public Backend { attr_properties = true; continue; } + if (args[argidx] == "-keep") { + keepmode = true; + continue; + } if (args[argidx] == "-pvector" && argidx+1 < args.size()) { std::string parray; port_rename = true; @@ -337,6 +344,71 @@ struct EdifBackend : public Backend { *f << stringf(" (view VIEW_NETLIST\n"); *f << stringf(" (viewType NETLIST)\n"); *f << stringf(" (interface\n"); + + for (auto cell : module->cells()) { + for (auto &conn : cell->connections()) + if (cell->output(conn.first)) + sigmap.add(conn.second); + } + + for (auto wire : module->wires()) + for (auto b1 : SigSpec(wire)) + { + auto b2 = sigmap(b1); + + if (b1 == b2 || !b2.wire) + continue; + + log_assert(b1.wire != nullptr); + + Wire *w1 = b1.wire; + Wire *w2 = b2.wire; + + { + int c1 = w1->get_bool_attribute(ID::keep); + int c2 = w2->get_bool_attribute(ID::keep); + + if (c1 > c2) goto promote; + if (c1 < c2) goto nopromote; + } + + { + int c1 = w1->name[0] == '\\'; + int c2 = w2->name[0] == '\\'; + + if (c1 > c2) goto promote; + if (c1 < c2) goto nopromote; + } + + { + auto count_nontrivial_attr = [](Wire *w) { + int count = w->attributes.size(); + count -= w->attributes.count(ID::src); + count -= w->attributes.count(ID::unused_bits); + return count; + }; + + int c1 = count_nontrivial_attr(w1); + int c2 = count_nontrivial_attr(w2); + + if (c1 > c2) goto promote; + if (c1 < c2) goto nopromote; + } + + { + int c1 = w1->port_id ? INT_MAX - w1->port_id : 0; + int c2 = w2->port_id ? INT_MAX - w2->port_id : 0; + + if (c1 > c2) goto promote; + if (c1 < c2) goto nopromote; + } + + nopromote: + if (0) + promote: + sigmap.add(b1); + } + for (auto wire : module->wires()) { if (wire->port_id == 0) continue; @@ -369,12 +441,15 @@ struct EdifBackend : public Backend { } } } + *f << stringf(" )\n"); *f << stringf(" (contents\n"); + if (!nogndvcc) { *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n"); *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); } + for (auto cell : module->cells()) { *f << stringf(" (instance %s\n", EDIF_DEF(cell->name)); *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), @@ -412,6 +487,7 @@ struct EdifBackend : public Backend { } } } + for (auto &it : net_join_db) { RTLIL::SigBit sig = it.first; if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) { @@ -440,7 +516,7 @@ struct EdifBackend : public Backend { } *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) - *f << stringf(" %s\n", ref.first.c_str()); + *f << stringf(" %s\n", ref.first.c_str()); if (sig.wire == NULL) { if (nogndvcc) log_error("Design contains constant nodes (map with \"hilomap\" first).\n"); @@ -455,30 +531,48 @@ struct EdifBackend : public Backend { add_prop(p.first, p.second); *f << stringf("\n )\n"); } - for (auto wire : module->wires()) { + + for (auto wire : module->wires()) + { if (!wire->get_bool_attribute(ID::keep)) continue; - for(int i = 0; i < wire->width; i++) { + + for(int i = 0; i < wire->width; i++) + { SigBit raw_sig = RTLIL::SigSpec(wire, i); SigBit mapped_sig = sigmap(raw_sig); + if (raw_sig == mapped_sig || net_join_db.count(mapped_sig) == 0) continue; + std::string netname = log_signal(raw_sig); for (size_t i = 0; i < netname.size(); i++) if (netname[i] == ' ' || netname[i] == '\\') netname.erase(netname.begin() + i--); - *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); - auto &refs = net_join_db.at(mapped_sig); - for (auto &ref : refs) - if (ref.second) - *f << stringf(" %s\n", ref.first.c_str()); - *f << stringf(" )"); - if (attr_properties && raw_sig.wire != NULL) - for (auto &p : raw_sig.wire->attributes) - add_prop(p.first, p.second); - *f << stringf("\n )\n"); + + if (keepmode) + { + *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); + + auto &refs = net_join_db.at(mapped_sig); + for (auto &ref : refs) + if (ref.second) + *f << stringf(" %s\n", ref.first.c_str()); + *f << stringf(" )"); + + if (attr_properties && raw_sig.wire != NULL) + for (auto &p : raw_sig.wire->attributes) + add_prop(p.first, p.second); + + *f << stringf("\n )\n"); + } + else + { + log_warning("Ignoring conflicting 'keep' property on net %s. Use -keep to generate the extra net nevertheless.\n", EDIF_DEF(netname)); + } } } + *f << stringf(" )\n"); *f << stringf(" )\n"); *f << stringf(" )\n"); |