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* techmap inside map_cells stageEddie Hung2019-04-052-2/+1
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* Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * Missing techmap entry in helpEddie Hung2019-04-041-0/+1
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* | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
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* | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-042-13/+13
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| * synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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| * Merge pull request #913 from smunaut/fix_proc_muxEddie Hung2019-04-031-1/+1
| |\ | | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
| | * proc_mux: Fix crash when trying to optimize non-existant mux to shiftxSylvain Munaut2019-04-031-1/+1
| |/ | | | | | | | | | | last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Cleanup commentsEddie Hung2019-04-041-5/+4
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* | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
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* | Remove handling for $pmux, since #895Eddie Hung2019-04-031-40/+0
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* | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
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* | Remove duplicate STARTUPE2Eddie Hung2019-04-031-1/+0
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* | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
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* | Add changelog entryEddie Hung2019-04-031-0/+1
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* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-0314-73/+526
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| * Merge pull request #912 from YosysHQ/bram_addr_enClifford Wolf2019-04-031-0/+2
| |\ | | | | | | memory_bram: Consider read enable for address expansion register
| | * memory_bram: Consider read enable for address expansion registerDavid Shah2019-04-021-0/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Merge pull request #910 from ucb-bar/memupdatesClifford Wolf2019-04-031-30/+173
| |\ \ | | |/ | |/| Refine memory support to deal with general Verilog memory definitions.
| | * Refine memory support to deal with general Verilog memory definitions.Jim Lawson2019-04-011-30/+173
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| * | Merge pull request #895 from YosysHQ/pmux2shiftxEddie Hung2019-04-021-0/+28
| |\ \ | | |/ | |/| RFC: Add a pmux-to-shiftx optimisation to proc_mux
| | * Create one $shiftx per bit in widthEddie Hung2019-03-251-10/+17
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| | * Add a pmux-to-shiftx optimisation to proc_muxEddie Hung2019-03-231-0/+21
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| * | Merge pull request #907 from YosysHQ/clifford/fix906Clifford Wolf2019-03-301-0/+2
| |\ \ | | | | | | | | Build Verilog parser with -DYYMAXDEPTH=100000
| | * | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #901 from trcwm/libertyfixesClifford Wolf2019-03-284-9/+151
| |\ \ | | | | | | | | Libertyfixes: accept superfluous ; at end of group.
| | * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
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| | * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
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| | * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-274-9/+151
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| * | | Merge pull request #903 from YosysHQ/bram_reset_transpClifford Wolf2019-03-281-0/+1
| |\ \ \ | | |/ / | |/| | memory_bram: Reset make_transp when growing read ports
| | * | memory_bram: Reset make_transp when growing read portsDavid Shah2019-03-271-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Add "read -verific" and "read -noverific"Clifford Wolf2019-03-271-6/+28
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add "rename -output"Clifford Wolf2019-03-271-3/+23
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve "rename" help messageClifford Wolf2019-03-271-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add "cutpoint -undef"Clifford Wolf2019-03-261-10/+14
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add "hdlname" attributeClifford Wolf2019-03-262-0/+5
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-262-15/+93
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
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* | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-2515-37/+943
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| * | | Add "cutpoint" passClifford Wolf2019-03-252-0/+165
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #896 from YosysHQ/transp_fixesClifford Wolf2019-03-251-9/+16
| |\ \ | | | | | | | | memory_bram: Fix multiclock make_transp
| | * | memory_bram: Fix multiclock make_transpDavid Shah2019-03-241-9/+16
| | |/ | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Merge pull request #897 from trcwm/libertyfixesClifford Wolf2019-03-258-22/+645
| |\ \ | | |/ | |/| Liberty parser: Accept ranges [A:B], and ignore missing ';'.
| | * spaces -> tabsNiels Moseley2019-03-251-78/+78
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| | * EOL is now accepted as ';' replacement on lines that look like: ↵Niels Moseley2019-03-251-4/+3
| | | | | | | | | | | | feature_xyz(option)
| | * Updated the liberty parser to accept [A:B] ranges (AST has not been ↵Niels Moseley2019-03-248-7/+631
| |/ | | | | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
| * Add "mutate -none -mode", "mutate -mode none"Clifford Wolf2019-03-231-1/+30
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "mutate -s <filename>"Clifford Wolf2019-03-231-2/+24
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #893 from YosysHQ/clifford/btormeminitClifford Wolf2019-03-233-3/+63
| |\ | | | | | | Memory init support in write_btor
| | * Add support for memory initialization to write_btorClifford Wolf2019-03-231-0/+53
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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