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Age
Files
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*
Improve tests to check that clkbuf is connected to expected
Eddie Hung
2019-08-26
1
-6
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+21
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-26
8
-60
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+405
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Remove dupe in CHANGELOG, missing end quote
Eddie Hung
2019-08-26
1
-2
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+1
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Merge tag 'yosys-0.9'
Clifford Wolf
2019-08-26
2
-11
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+107
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Yosys 0.9
Clifford Wolf
2019-08-26
1
-1
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+1
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Revert earliest to gcc-4.8, compile iverilog with default compiler
Eddie Hung
2019-08-23
2
-3
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+3
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Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"
Eddie Hung
2019-08-23
1
-5
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+3
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Remove .0 from clang-8.0
Eddie Hung
2019-08-23
1
-2
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+2
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Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!
Eddie Hung
2019-08-23
1
-3
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+5
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bionic -> xenial as its on whitelist
Eddie Hung
2019-08-23
1
-1
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+1
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Bump gcc from 4.8 to 4.9 as undefined reference
Eddie Hung
2019-08-23
1
-35
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+7
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Make macOS depenency clear
Miodrag Milanovic
2019-08-23
1
-2
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+5
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do not require boost if pyosys is not used
Miodrag Milanovic
2019-08-22
1
-0
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+2
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require tcl-tk in Brewfile
Chris Shucksmith
2019-08-22
1
-0
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+1
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Bump year in copyright notice
Clifford Wolf
2019-08-22
3
-3
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+3
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Visual Studio build fix
Miodrag Milanovic
2019-08-02
1
-0
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+1
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Fix linking issue for new mxe and pthread
Miodrag Milanovic
2019-08-02
1
-1
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+2
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Fix yosys linking for mxe
Miodrag Milanovic
2019-08-02
1
-1
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+1
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New mxe hacks needed to support 2ca237e
Miodrag Milanovic
2019-08-02
1
-0
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+4
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Fix formatting for msys2 mingw build using GetSize
Miodrag Milanovic
2019-08-02
8
-17
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+20
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Update CHANGELOG
David Shah
2019-07-26
1
-10
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+101
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Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
Clifford Wolf
2019-07-09
1
-3
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+2
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Update CHANGELOG
David Shah
2019-07-09
1
-0
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+1
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Merge pull request #1163 from whitequark/more-case-attrs
Clifford Wolf
2019-07-09
3
-16
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+28
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Merge pull request #1162 from whitequark/rtlil-case-attrs
Clifford Wolf
2019-07-09
3
-5
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+15
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Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire
Clifford Wolf
2019-07-09
1
-0
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+3
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Merge pull request #1147 from YosysHQ/clifford/fix1144
Clifford Wolf
2019-07-09
3
-82
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+26
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Merge pull request #1154 from whitequark/manual-sync-always
Clifford Wolf
2019-07-09
1
-2
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+3
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Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
David Shah
2019-07-09
3
-3
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+25
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Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...
Clifford Wolf
2019-07-09
1
-0
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+2
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autotest.sh to define _AUTOTB when test_autotb
Eddie Hung
2019-07-09
1
-1
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+1
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Merge pull request #1146 from gsomlo/gls-test-abc-ext
Clifford Wolf
2019-07-09
4
-8
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+29
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Checkout yosys-0.9-rc branch of yosys-tests
Eddie Hung
2019-07-02
1
-1
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+1
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Add missing CHANGELOG entries
Eddie Hung
2019-06-28
1
-0
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+3
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Merge pull request #1112 from acw1251/pyosys_sigsig_issue
Clifford Wolf
2019-08-25
1
-16
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+10
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Fixed pyosys commands returning RTLIL::SigSig
acw1251
2019-06-19
1
-16
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+10
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Merge pull request #1327 from YosysHQ/clifford/pmgen
Clifford Wolf
2019-08-24
5
-32
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+280
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indo -> into
Eddie Hung
2019-08-23
1
-1
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+1
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Fix port hanlding in pmgen
Clifford Wolf
2019-08-23
1
-4
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+3
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Add pmgen slices and choices
Clifford Wolf
2019-08-23
5
-28
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+277
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Add undocumented feature
Eddie Hung
2019-08-23
1
-0
/
+8
*
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
-1
/
+1
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Forgot one
Eddie Hung
2019-08-23
1
-1
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+2
*
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
3
-18
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+36
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Put abc_* attributes above port
Eddie Hung
2019-08-23
3
-14
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+28
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Check clkbuf_inhibit=1 is ignored for custom selection
Eddie Hung
2019-08-23
1
-0
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+1
*
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clkbufmap to only check clkbuf_inhibit if no selection given
Eddie Hung
2019-08-23
1
-5
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+18
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Add simple clkbufmap tests
Eddie Hung
2019-08-23
1
-0
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+52
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tests/techmap/run-test.sh to cope with *.ys
Eddie Hung
2019-08-23
2
-7
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+18
*
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Mention clkbuf_inhibit can be overridden
Eddie Hung
2019-08-23
1
-7
/
+8
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