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author | Clifford Wolf <clifford@clifford.at> | 2019-07-09 22:51:25 +0200 |
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committer | David Shah <dave@ds0.me> | 2019-07-09 22:19:34 +0100 |
commit | 1d58bbb79c36d88c24008797947789d9ae5605be (patch) | |
tree | cb379be34b0648213a600f0e761b7653cad0889a | |
parent | c8979a3353c531884fd7f7dec8c06682d0b4b3ec (diff) | |
download | yosys-1d58bbb79c36d88c24008797947789d9ae5605be.tar.gz yosys-1d58bbb79c36d88c24008797947789d9ae5605be.tar.bz2 yosys-1d58bbb79c36d88c24008797947789d9ae5605be.zip |
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
write_verilog: fix placement of case attributes
-rw-r--r-- | backends/verilog/verilog_backend.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6288502a5..087c6fec6 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1501,6 +1501,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw bool got_default = false; for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { + dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true); if ((*it)->compare.size() == 0) { if (got_default) continue; @@ -1514,9 +1515,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw dump_sigspec(f, (*it)->compare[i]); } } - f << stringf(":"); - dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true); - f << stringf("\n"); + f << stringf(":\n"); dump_case_body(f, indent + " ", *it); } |