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authorEddie Hung <eddie@fpgeh.com>2019-08-26 10:44:23 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-26 10:44:23 -0700
commitbd3773a17f220f1fa9b478b3785acac42ca3bd7f (patch)
treeacfc1b81b0e03397d622dd4b7baeab82bb3409a6
parent8a4c6e6563eea979dc96cada14abb08d63a8e3d1 (diff)
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Remove dupe in CHANGELOG, missing end quote
-rw-r--r--CHANGELOG3
1 files changed, 1 insertions, 2 deletions
diff --git a/CHANGELOG b/CHANGELOG
index c4882acab..113aae820 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -12,11 +12,10 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- - Added "script -scriptwire
+ - Added "script -scriptwire"
- Added "synth_xilinx -nocarry"
- Added "synth_xilinx -nowidelut"
- Added "synth_ecp5 -nowidelut"
- - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)