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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:10:02 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:10:02 -0700 |
commit | 5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d (patch) | |
tree | 0263ba8a7a24280e3c47dd7c0c02f6b939bd8c9f | |
parent | d62c10d641c5af4b1d395caa042681788df1aae4 (diff) | |
download | yosys-5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d.tar.gz yosys-5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d.tar.bz2 yosys-5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d.zip |
Add simple clkbufmap tests
-rw-r--r-- | tests/techmap/clkbufmap.ys | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys new file mode 100644 index 000000000..eb8970af4 --- /dev/null +++ b/tests/techmap/clkbufmap.ys @@ -0,0 +1,52 @@ +read_verilog <<EOT +module clkbuf (input i, (* clkbuf_driver *) output o); endmodule +module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule +module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule +module latch (input e, d, output q); endmodule + +module top(input clk1, clk2, clk3, d, e, output [2:0] q); +dff s0 (.clk(clk1), .d(d), .q(q[0])); +dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1])); +latch s2 (.e(clk3), .d(d), .q(q[2])); +endmodule +EOT + +hierarchy -auto-top +design -save ref + +# ---------------------- + +design -load ref +clkbufmap -buf clkbuf o:i +select -assert-count 1 w:clk1 %a %co t:clkbuf %i +select -assert-count 1 w:clk2 %a %co t:clkbuf %i +select -assert-count 2 t:clkbuf + +# ---------------------- + +design -load ref +setattr -set clkbuf_inhibit 0 w:clk1 +setattr -set clkbuf_inhibit 1 w:clk2 +clkbufmap -buf clkbuf o:i +select -assert-count 1 w:clk1 %a %co t:clkbuf %i +select -assert-count 0 w:clk2 %a %co t:clkbuf %i +select -assert-count 1 t:clkbuf + +# ---------------------- + +design -load ref +setattr -set buffer_type "bufg" w:clk2 +clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d +select -assert-count 1 w:clk1 %a %co t:clkbuf %i +select -assert-count 1 w:clk2 %a %co t:clkbuf %i +select -assert-count 2 t:clkbuf + +# ---------------------- + +design -load ref +setattr -set buffer_type "none" w:clk1 +setattr -set buffer_type "bufr" w:clk2 +clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d +select -assert-count 0 w:clk1 %a %co t:clkbuf %i +select -assert-count 0 w:clk2 %a %co t:clkbuf %i +select -assert-count 0 t:clkbuf |