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Age
Files
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*
use "hierarchy -auto-top" in synth_ice40
Clifford Wolf
2015-04-14
1
-3
/
+3
*
more cells in ice40 cell library
Clifford Wolf
2015-04-14
1
-8
/
+289
*
Added "splice -wires"
Clifford Wolf
2015-04-13
1
-9
/
+20
*
Added handling of bool-output cells to "wreduce"
Clifford Wolf
2015-04-13
1
-0
/
+11
*
Improved xilinx "bram1" test
Clifford Wolf
2015-04-09
1
-1
/
+2
*
Added memory_bram "make_outreg" feature
Clifford Wolf
2015-04-09
2
-2
/
+27
*
Added back-end auto-detect for .edif and .json
Clifford Wolf
2015-04-09
1
-0
/
+4
*
Minor fixes in handling of "init" attribute
Clifford Wolf
2015-04-09
2
-7
/
+12
*
Xilinx DRAMS: RAM64X1D, RAM128X1D
Clifford Wolf
2015-04-09
3
-13
/
+67
*
Fixed const2big performance bug
Clifford Wolf
2015-04-09
1
-14
/
+21
*
techmap code cleanup
Clifford Wolf
2015-04-09
1
-10
/
+6
*
Towards DRAM support in Xilinx flow
Clifford Wolf
2015-04-09
5
-0
/
+78
*
Added support for "file names with blanks"
Clifford Wolf
2015-04-08
7
-33
/
+43
*
Removed "techmap -share_map" (use "-map +/filename" instead)
Clifford Wolf
2015-04-08
2
-10
/
+1
*
Added %M and %C select operators
Clifford Wolf
2015-04-07
1
-1
/
+38
*
Added "pmuxtree" command
Clifford Wolf
2015-04-07
3
-0
/
+164
*
Added "chparam -list"
Clifford Wolf
2015-04-07
1
-0
/
+21
*
Added decoder generation to "muxcover"
Clifford Wolf
2015-04-07
1
-13
/
+104
*
Added hashlib support for std::tuple<>
Clifford Wolf
2015-04-07
1
-0
/
+15
*
Added "muxcover" command
Clifford Wolf
2015-04-07
2
-0
/
+542
*
Added pool<K>::pop()
Clifford Wolf
2015-04-07
1
-0
/
+8
*
typo fix
Clifford Wolf
2015-04-07
1
-1
/
+1
*
Added "chparam" command
Clifford Wolf
2015-04-07
1
-0
/
+57
*
Added support for initialized xilinx brams
Clifford Wolf
2015-04-06
11
-92
/
+315
*
Added support for initialized brams
Clifford Wolf
2015-04-06
2
-9
/
+45
*
Added Xilinx test case for initialized brams
Clifford Wolf
2015-04-06
4
-0
/
+80
*
Added Xilinx bram black-box modules
Clifford Wolf
2015-04-06
3
-0
/
+322
*
Added "port_directions" to write_json output
Clifford Wolf
2015-04-06
1
-0
/
+20
*
Avoid parameter values with size 0 ($mem cells)
Clifford Wolf
2015-04-05
3
-11
/
+16
*
make all vector-size related integer params in $mem sim model signed
Clifford Wolf
2015-04-05
1
-6
/
+6
*
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
Clifford Wolf
2015-04-05
4
-2
/
+131
*
Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
6
-8
/
+132
*
Added "init" attribute support to verilog backend
Clifford Wolf
2015-04-04
1
-0
/
+5
*
appnote 012 fix
Clifford Wolf
2015-04-04
1
-2
/
+2
*
Appnote 012
Clifford Wolf
2015-04-04
2
-115
/
+115
*
Updated ABC to 51705b168d7a
Clifford Wolf
2015-04-04
1
-2
/
+2
*
Merge pull request #55 from ahmedirfan1983/master
Clifford Wolf
2015-04-04
4
-27
/
+492
|
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*
Update README
Ahmed Irfan
2015-04-03
1
-1
/
+1
|
*
Delete btor.ys
Ahmed Irfan
2015-04-03
1
-18
/
+0
|
*
Update README
Ahmed Irfan
2015-04-03
1
-1
/
+1
|
*
separated memory next from write cell
Ahmed Irfan
2015-04-03
1
-7
/
+55
|
*
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Ahmed Irfan
2015-04-03
266
-4671
/
+18443
|
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/
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/
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*
|
documentation improvements
Clifford Wolf
2015-03-29
2
-1
/
+5
*
|
Ignore celldefine directive in verilog front-end
Clifford Wolf
2015-03-25
1
-0
/
+3
*
|
Fixes in cmos_cells.v
Clifford Wolf
2015-03-25
1
-3
/
+12
*
|
Fixed detection of absolute paths in ABC for win32
Clifford Wolf
2015-03-22
3
-3
/
+13
*
|
Added blif reference to appnote 010
Clifford Wolf
2015-03-22
1
-1
/
+5
*
|
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2015-03-20
1
-2
/
+2
|
\
\
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*
|
Fixed handling of quotes in liberty parser
Clifford Wolf
2015-03-18
1
-2
/
+2
*
|
|
fix for python 2.6.6
Clifford Wolf
2015-03-20
3
-165
/
+172
|
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