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| author | Clifford Wolf <clifford@clifford.at> | 2015-03-25 19:46:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-03-25 19:46:12 +0100 |
| commit | a923a63a892b8f0c39aa740c8fe207462fe2d8c8 (patch) | |
| tree | ad5a170887620f00c91672c3d2394306527d7641 | |
| parent | e468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9 (diff) | |
| download | yosys-a923a63a892b8f0c39aa740c8fe207462fe2d8c8.tar.gz yosys-a923a63a892b8f0c39aa740c8fe207462fe2d8c8.tar.bz2 yosys-a923a63a892b8f0c39aa740c8fe207462fe2d8c8.zip | |
Ignore celldefine directive in verilog front-end
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 3a57514aa..8fbaa953d 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -116,6 +116,9 @@ YOSYS_NAMESPACE_END "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */ +"`celldefine"[^\n]* /* ignore `celldefine */ +"`endcelldefine"[^\n]* /* ignore `endcelldefine */ + "`default_nettype"[ \t]+[^ \t\r\n/]+ { char *p = yytext; while (*p != 0 && *p != ' ' && *p != '\t') p++; |