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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-14 13:45:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-14 13:45:15 +0200 |
| commit | 4529c56cc67042235c80e337c92ead2d154da1c4 (patch) | |
| tree | e777a4cb1c5e7b2a55975bde10d8031a4a6d1dd8 | |
| parent | 06ce496f8da61d81f2c1abd4f6c4977c55a0d4b6 (diff) | |
| download | yosys-4529c56cc67042235c80e337c92ead2d154da1c4.tar.gz yosys-4529c56cc67042235c80e337c92ead2d154da1c4.tar.bz2 yosys-4529c56cc67042235c80e337c92ead2d154da1c4.zip | |
use "hierarchy -auto-top" in synth_ice40
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 8c98c4b27..2fe921407 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -85,14 +85,14 @@ struct SynthIce40Pass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - std::string top_module = "top"; + std::string top_opt = "-auto-top"; std::string run_from, run_to; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-top" && argidx+1 < args.size()) { - top_module = args[++argidx]; + top_opt = "-top " + args[++argidx]; continue; } if (args[argidx] == "-run" && argidx+1 < args.size()) { @@ -118,7 +118,7 @@ struct SynthIce40Pass : public Pass { if (check_label(active, run_from, run_to, "begin")) { Pass::call(design, "read_verilog -lib +/ice40/cells_sim.v"); - Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str())); + Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); } if (check_label(active, run_from, run_to, "coarse")) |