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authorClifford Wolf <clifford@clifford.at>2015-04-05 17:26:53 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-05 17:26:53 +0200
commit95944eb69e45837516ff9c0cba54f77ab89af754 (patch)
tree20dabb0609e67176b85461f5d78350506d76eb99
parent706631225e9ef0d2954c4bef51aaa2817e0f5e86 (diff)
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make all vector-size related integer params in $mem sim model signed
this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
-rw-r--r--techlibs/common/simlib.v12
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index abd2af521..f3a127170 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1556,18 +1556,18 @@ endmodule
module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";
-parameter SIZE = 4;
-parameter OFFSET = 0;
-parameter ABITS = 2;
-parameter WIDTH = 8;
+parameter signed SIZE = 4;
+parameter signed OFFSET = 0;
+parameter signed ABITS = 2;
+parameter signed WIDTH = 8;
parameter signed INIT = 1'bx;
-parameter RD_PORTS = 1;
+parameter signed RD_PORTS = 1;
parameter RD_CLK_ENABLE = 1'b1;
parameter RD_CLK_POLARITY = 1'b1;
parameter RD_TRANSPARENT = 1'b1;
-parameter WR_PORTS = 1;
+parameter signed WR_PORTS = 1;
parameter WR_CLK_ENABLE = 1'b1;
parameter WR_CLK_POLARITY = 1'b1;