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* Add -hidden option to submodEddie Hung2019-11-261-11/+25
* Update docs with bullet pointsEddie Hung2019-11-261-10/+9
* Move \init from source wire to submod if output portEddie Hung2019-11-251-0/+7
* Add testcase where \init is copiedEddie Hung2019-11-251-0/+18
* Remove redundant flattenEddie Hung2019-11-221-2/+0
* submod to bitty rather bussy, for bussy wires used as input and outputEddie Hung2019-11-221-48/+39
* Stray dumpEddie Hung2019-11-221-1/+0
* Constant driven signals are also an input to submodulesEddie Hung2019-11-221-2/+10
* Add another test with constant driverEddie Hung2019-11-221-0/+28
* OopsEddie Hung2019-11-221-1/+0
* Cleanup spacingEddie Hung2019-11-221-2/+1
* sigmap(wire) should inherit port_output status of POsEddie Hung2019-11-221-1/+19
* Add testcaseEddie Hung2019-11-221-0/+26
* Merge pull request #1517 from YosysHQ/clifford/optmemClifford Wolf2019-11-223-0/+146
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| * Add "opt_mem" passClifford Wolf2019-11-223-0/+146
* | Merge pull request #1515 from YosysHQ/clifford/svastuffClifford Wolf2019-11-222-7/+39
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| * Add Verific support for SVA nexttime propertiesClifford Wolf2019-11-221-0/+22
| * Improve handling of verific primitives in "verific -import -V" modeClifford Wolf2019-11-221-2/+2
| * Add Verific SVA support for "always" propertiesClifford Wolf2019-11-221-5/+15
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* Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-226-9/+126
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| * Update CHANGELOG and READMEDavid Shah2019-11-222-0/+7
| * sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
| * proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usageDavid Shah2019-11-211-4/+16
| * sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
* | gowin: Remove show command from tests.Marcin Kościelnicki2019-11-221-1/+0
* | gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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* Merge pull request #1507 from YosysHQ/clifford/verificfixesClifford Wolf2019-11-202-6/+9
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| * Correctly treat empty modules as blackboxes in VerificClifford Wolf2019-11-201-1/+1
| * Do not rename VHDL entities to "entity(impl)" when they are top modulesClifford Wolf2019-11-202-5/+8
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* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1927-89/+841
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| * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1615-47/+913
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-112-4/+15
| * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1129-23010/+30701
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| * | | fix wide lutsPepijn de Vos2019-11-062-19/+22
| * | | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
| * | | add IOBUFPepijn de Vos2019-10-282-1/+10
| * | | add tristate buffer and testPepijn de Vos2019-10-283-2/+21
| * | | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
| * | | actually run the gowin testsPepijn de Vos2019-10-281-0/+1
| * | | More formattingPepijn de Vos2019-10-281-55/+49
| * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
| * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
| * | | add wide lutsPepijn de Vos2019-10-283-36/+119
| * | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
| * | | ALU sim tweaksPepijn de Vos2019-10-242-13/+13
| * | | Add some testsPepijn de Vos2019-10-2110-0/+224
| * | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
| * | | add negedge DFFPepijn de Vos2019-10-212-15/+139
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